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| author | Seth LaForge <sethml@google.com> | 2014-04-01 10:26:32 -0700 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2014-04-14 18:20:36 +0000 |
| commit | 3427cf2b7e33240fc63c6398090dc7bcbf4f2d52 (patch) | |
| tree | b2ee5f131d6d2250908f0601199e3c65fdf4bbdf /tcl/target | |
| parent | 31496c2bedd367ea4282328da42c997c85d67c2e (diff) | |
| download | riscv-openocd-3427cf2b7e33240fc63c6398090dc7bcbf4f2d52.zip riscv-openocd-3427cf2b7e33240fc63c6398090dc7bcbf4f2d52.tar.gz riscv-openocd-3427cf2b7e33240fc63c6398090dc7bcbf4f2d52.tar.bz2 | |
cortex_a: fix endiannes issues on TI TMS570
The TI TMS470 and TMS570 series of processors are BE-32 processors,
despite BE-32 not being supported by ARM in the Cortex-R4 core. TI
hacked in BE-32 support, which requires odd swizzling in OpenOCD to
make memory reads and writes function correctly. In particular,
without this change, OpenOCD word reads and writes had the bytes
reversed, and halfword and byte packed reads were reading garbage.
In my testing, this change fixes these problems.
Change-Id: I21dd30f4b9003f20fcc85f674ab833407bb61f74
Signed-off-by: Seth LaForge <sethml@google.com>
Reviewed-on: http://openocd.zylin.com/2064
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/ti_tms570.cfg | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/tcl/target/ti_tms570.cfg b/tcl/target/ti_tms570.cfg index 589e9d6..014c76c 100644 --- a/tcl/target/ti_tms570.cfg +++ b/tcl/target/ti_tms570.cfg @@ -40,6 +40,9 @@ set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \ -chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003 +# TMS570 uses quirky BE-32 mode +$_TARGETNAME dap ti_be_32_quirks 1 + $_TARGETNAME configure -event gdb-attach { cortex_r4 dbginit halt |