diff options
| author | Spencer Oliver <spen@spen-soft.co.uk> | 2012-08-23 21:03:29 +0100 |
|---|---|---|
| committer | Freddie Chopin <freddie.chopin@gmail.com> | 2012-08-29 06:24:36 +0000 |
| commit | 2ce4e31bbcfabc06b7ac71d2e507e707d293c5c0 (patch) | |
| tree | 2b6686f334bcb1d0123fa204938d6a419a7348de /tcl/target | |
| parent | 4be685c6167e8ac340cd383f0a0a61faaa45f3f8 (diff) | |
| download | riscv-openocd-2ce4e31bbcfabc06b7ac71d2e507e707d293c5c0.zip riscv-openocd-2ce4e31bbcfabc06b7ac71d2e507e707d293c5c0.tar.gz riscv-openocd-2ce4e31bbcfabc06b7ac71d2e507e707d293c5c0.tar.bz2 | |
cfg: update for target's that support cortex_m AIRCR SYSRESETREQ
If the target supports SYSRESETREQ make sure we use that as the default
if srst is not fitted/configured.
Change-Id: I24c907493134506320e69c1218702930629c1cdc
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/792
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/at91sam3XXX.cfg | 4 | ||||
| -rw-r--r-- | tcl/target/at91sam3nXX.cfg | 5 | ||||
| -rw-r--r-- | tcl/target/at91sam4XXX.cfg | 4 | ||||
| -rw-r--r-- | tcl/target/k40.cfg | 4 | ||||
| -rw-r--r-- | tcl/target/k60.cfg | 4 | ||||
| -rw-r--r-- | tcl/target/lpc17xx.cfg | 4 | ||||
| -rw-r--r-- | tcl/target/lpc4350.cfg | 4 |
7 files changed, 29 insertions, 0 deletions
diff --git a/tcl/target/at91sam3XXX.cfg b/tcl/target/at91sam3XXX.cfg index 63759e3..b90e3f0 100644 --- a/tcl/target/at91sam3XXX.cfg +++ b/tcl/target/at91sam3XXX.cfg @@ -66,3 +66,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-ar $_TARGETNAME configure -event gdb-flash-erase-start { halt } + +# if srst is not fitted use SYSRESETREQ to +# perform a soft reset +cortex_m3 reset_config sysresetreq diff --git a/tcl/target/at91sam3nXX.cfg b/tcl/target/at91sam3nXX.cfg index 9e362b2..b628103 100644 --- a/tcl/target/at91sam3nXX.cfg +++ b/tcl/target/at91sam3nXX.cfg @@ -22,3 +22,8 @@ target create $_TARGETNAME cortex_m3 -endian little -chain-position $_TARGETNAME set _FLASHNAME $_CHIPNAME.flash flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME + +# if srst is not fitted use SYSRESETREQ to +# perform a soft reset +cortex_m3 reset_config sysresetreq + diff --git a/tcl/target/at91sam4XXX.cfg b/tcl/target/at91sam4XXX.cfg index d9f5746..c341218 100644 --- a/tcl/target/at91sam4XXX.cfg +++ b/tcl/target/at91sam4XXX.cfg @@ -43,3 +43,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-ar $_TARGETNAME configure -event gdb-flash-erase-start { halt } + +# if srst is not fitted use SYSRESETREQ to +# perform a soft reset +cortex_m3 reset_config sysresetreq diff --git a/tcl/target/k40.cfg b/tcl/target/k40.cfg index 26b952b..57aa849 100644 --- a/tcl/target/k40.cfg +++ b/tcl/target/k40.cfg @@ -33,3 +33,7 @@ target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu $_CHIPNAME.cpu configure -event examine-start { puts "START..." ; } $_CHIPNAME.cpu configure -event examine-end { puts "END..." ; } + +# if srst is not fitted use SYSRESETREQ to +# perform a soft reset +cortex_m3 reset_config sysresetreq diff --git a/tcl/target/k60.cfg b/tcl/target/k60.cfg index d1247f3..a85fa90 100644 --- a/tcl/target/k60.cfg +++ b/tcl/target/k60.cfg @@ -33,3 +33,7 @@ target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu $_CHIPNAME.cpu configure -event examine-start { puts "START..." ; } $_CHIPNAME.cpu configure -event examine-end { puts "END..." ; } + +# if srst is not fitted use SYSRESETREQ to +# perform a soft reset +cortex_m3 reset_config sysresetreq diff --git a/tcl/target/lpc17xx.cfg b/tcl/target/lpc17xx.cfg index 379bcfb..a64783d 100644 --- a/tcl/target/lpc17xx.cfg +++ b/tcl/target/lpc17xx.cfg @@ -91,3 +91,7 @@ $_TARGETNAME configure -event reset-init { mww 0x400FC040 0x01 } + +# if srst is not fitted use VECTRESET to +# perform a soft reset - SYSRESETREQ is not supported +cortex_m3 reset_config vectreset diff --git a/tcl/target/lpc4350.cfg b/tcl/target/lpc4350.cfg index 63d1307..6614383 100644 --- a/tcl/target/lpc4350.cfg +++ b/tcl/target/lpc4350.cfg @@ -42,3 +42,7 @@ jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \ target create $_CHIPNAME.m4 cortex_m3 -chain-position $_CHIPNAME.m4 target create $_CHIPNAME.m0 cortex_m3 -chain-position $_CHIPNAME.m0 + +# if srst is not fitted use SYSRESETREQ to +# perform a soft reset +cortex_m3 reset_config sysresetreq |