Merge pull request #494 from riscv/from_upstream

Get changes from upstream

162 files changed, 1429 insertions, 441 deletions

diff --git a/tcl/target/1986Be1T.cfg b/tcl/target/1986Be1T.cfg
index ecb3f8a..b7c9d63 100644
--- a/tcl/target/1986Be1T.cfg
+++ b/tcl/target/1986Be1T.cfg
@@ -50,9 +50,9 @@ if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
 }
 
 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
    jtag_ntrst_delay 100
 }
diff --git a/tcl/target/K1879x61R.cfg b/tcl/target/K1879x61R.cfg
index 7d8c113..0a8467f 100644
--- a/tcl/target/K1879x61R.cfg
+++ b/tcl/target/K1879x61R.cfg
@@ -1,7 +1,7 @@
 # СБИС К1879ХБ1Я
 # http://www.module.ru/catalog/micro/mikroshema_dekodera_cifrovogo_televizionnogo_signala_sbis_k1879hb1ya/
 
-adapter_khz 1000
+adapter speed 1000
 
 if { [info exists CHIPNAME] } {
     set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/adsp-sc58x.cfg b/tcl/target/adsp-sc58x.cfg
index 8c9ef12..6073bb2 100644
--- a/tcl/target/adsp-sc58x.cfg
+++ b/tcl/target/adsp-sc58x.cfg
@@ -50,4 +50,3 @@ proc sc58x_enabledebug {} {
    # it is not possible to halt the target unless these bits have been set
    ap0.mem mww 0x31131000 0xFFFF
 }
-
diff --git a/tcl/target/aduc702x.cfg b/tcl/target/aduc702x.cfg
index fca0a7f..9c756be 100644
--- a/tcl/target/aduc702x.cfg
+++ b/tcl/target/aduc702x.cfg
@@ -17,7 +17,7 @@ if { [info exists CPUTAPID] } {
    set _CPUTAPID 0x3f0f0f0f
 }
 
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
 
 ## JTAG scan chain
diff --git a/tcl/target/aducm360.cfg b/tcl/target/aducm360.cfg
index ca4bc68..b381728 100755..100644
--- a/tcl/target/aducm360.cfg
+++ b/tcl/target/aducm360.cfg
@@ -10,7 +10,7 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME aducm360
 }
 
-# Endianess
+# Endianness
 if { [info exists ENDIAN] } {
    set _ENDIAN $ENDIAN
 } else {
@@ -36,7 +36,7 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 # SWD/JTAG speed
-adapter_khz 1000
+adapter speed 1000
 
 ##
 ## Target configuration
@@ -51,6 +51,6 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME aducm360 0x00 0 0 0 $_TARGETNAME
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 cortex_m reset_config sysresetreq
diff --git a/tcl/target/allwinner_v3s.cfg b/tcl/target/allwinner_v3s.cfg
index 32fd188..d8d78bd 100644
--- a/tcl/target/allwinner_v3s.cfg
+++ b/tcl/target/allwinner_v3s.cfg
@@ -34,7 +34,7 @@
 # 0220ms	JTAG pins switched to SD mode
 #
 # The time frame of 20ms can be not enough to init and halt the CPU. In this
-# case I would recommend to set: "adapter_khz 15000"
+# case I would recommend to set: "adapter speed 15000"
 # To get more or less precise timings, the board should provide reset pin,
 # or some bench power supply with remote function. In my case I used
 # EEZ H24005 with this command to power on and halt the target:
diff --git a/tcl/target/altera_fpgasoc.cfg b/tcl/target/altera_fpgasoc.cfg
index 9a83b5c..0fc8d67 100644
--- a/tcl/target/altera_fpgasoc.cfg
+++ b/tcl/target/altera_fpgasoc.cfg
@@ -36,7 +36,7 @@ jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-
 # core 1  -  0x80112000
 
 # Slow speed to be sure it will work
-adapter_khz 1000
+adapter speed 1000
 
 set _TARGETNAME1 $_CHIPNAME.cpu.0
 set _TARGETNAME2 $_CHIPNAME.cpu.1
@@ -46,7 +46,7 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap \
         -coreid 0 -dbgbase 0x80110000
 
-$_TARGETNAME1 configure -event reset-start { adapter_khz 1000 }
+$_TARGETNAME1 configure -event reset-start { adapter speed 1000 }
 $_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
 
 
@@ -54,7 +54,7 @@ $_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
 #target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap \
 #        -coreid 1 -dbgbase 0x80112000
 
-#$_TARGETNAME2 configure -event reset-start { adapter_khz 1000 }
+#$_TARGETNAME2 configure -event reset-start { adapter speed 1000 }
 #$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
 
 proc cycv_dbginit {target} {
diff --git a/tcl/target/amdm37x.cfg b/tcl/target/amdm37x.cfg
index 5c4e315..3db24b4 100644
--- a/tcl/target/amdm37x.cfg
+++ b/tcl/target/amdm37x.cfg
@@ -45,7 +45,7 @@ if { [info exists CHIPTYPE] } {
 
 # Run the adapter at the fastest acceptable speed with the slowest possible
 # core clock.
-adapter_khz 10
+adapter speed 10
 
 ###############################################################################
 # JTAG setup
@@ -157,7 +157,7 @@ $_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
 #  slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
 #  *after* PLL and clock tree setup.
 
-$_TARGETNAME configure -event "reset-start" { adapter_khz 10 }
+$_TARGETNAME configure -event "reset-start" { adapter speed 10 }
 
 # Describe the reset assert process for openocd - this is asserted with the
 # ICEPick
@@ -176,7 +176,7 @@ $_TARGETNAME configure -event reset-assert-post {
 
    global _TARGETNAME
    amdm37x_dbginit $_TARGETNAME
-   adapter_khz 1000
+   adapter speed 1000
 }
 
 $_TARGETNAME configure -event gdb-attach {
@@ -209,4 +209,3 @@ proc amdm37x_dbginit {target} {
    # at this address and this bit.
    $target mww phys 0x5401d030 0x00002000
 }
-
diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg
index 196b048..57833f4 100644
--- a/tcl/target/ar71xx.cfg
+++ b/tcl/target/ar71xx.cfg
@@ -1,7 +1,7 @@
 # Atheros AR71xx MIPS 24Kc SoC.
 # tested on PB44 refererence board
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 reset_config trst_and_srst
@@ -54,4 +54,3 @@ $_TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
 
 # serial SPI capable flash
 # flash bank <driver> <base> <size> <chip_width> <bus_width>
-
diff --git a/tcl/target/armada370.cfg b/tcl/target/armada370.cfg
index 5b84637..3b4be9f 100644
--- a/tcl/target/armada370.cfg
+++ b/tcl/target/armada370.cfg
@@ -31,4 +31,3 @@ $_TARGETNAME configure -event reset-assert-post "armada370_dbginit $_TARGETNAME"
 # We need to init now, so we can run the apsel command.
 init
 dap apsel 1
-
diff --git a/tcl/target/at91rm9200.cfg b/tcl/target/at91rm9200.cfg
index 2e8c1e0..3d9a8d9 100644
--- a/tcl/target/at91rm9200.cfg
+++ b/tcl/target/at91rm9200.cfg
@@ -28,7 +28,7 @@ if { $_CPUTAPID == 0x15b0203f } {
    echo "- ERROR:                                              -"
    echo "- ERROR: In one position (0x05b0203f) it selects the  -"
    echo "- ERROR: ARM CPU, in the other position (0x1b0203f)   -"
-   echo "- ERROR: it selects boundry-scan not the ARM          -"
+   echo "- ERROR: it selects boundary-scan not the ARM         -"
    echo "- ERROR:                                              -"
    echo "-------------------------------------------------------"
 }
diff --git a/tcl/target/at91sam3XXX.cfg b/tcl/target/at91sam3XXX.cfg
index e7dec4b..7d01ccd 100644
--- a/tcl/target/at91sam3XXX.cfg
+++ b/tcl/target/at91sam3XXX.cfg
@@ -74,9 +74,9 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
 
-adapter_khz 500
+adapter speed 500
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
    jtag_ntrst_delay 100
 }
diff --git a/tcl/target/at91sam3ax_8x.cfg b/tcl/target/at91sam3ax_8x.cfg
index e249383..2bb66fb 100644
--- a/tcl/target/at91sam3ax_8x.cfg
+++ b/tcl/target/at91sam3ax_8x.cfg
@@ -7,5 +7,3 @@ flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
 # This is a 512K chip - it has the 2nd bank
 set _FLASHNAME $_CHIPNAME.flash1
 flash bank $_FLASHNAME at91sam3 0x0000C0000 0 1 1 $_TARGETNAME
-
-
diff --git a/tcl/target/at91sam3ax_xx.cfg b/tcl/target/at91sam3ax_xx.cfg
index e561771..5e01d66 100644
--- a/tcl/target/at91sam3ax_xx.cfg
+++ b/tcl/target/at91sam3ax_xx.cfg
@@ -8,4 +8,3 @@
 # at91sam3X8E
 # at91sam3X8H
 source [find target/at91sam3XXX.cfg]
-
diff --git a/tcl/target/at91sam3u1c.cfg b/tcl/target/at91sam3u1c.cfg
index 47c227b..dc5c82c 100644
--- a/tcl/target/at91sam3u1c.cfg
+++ b/tcl/target/at91sam3u1c.cfg
@@ -4,5 +4,3 @@ source [find target/at91sam3uxx.cfg]
 # size is automatically "calculated" by probing
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
-
-
diff --git a/tcl/target/at91sam3u1e.cfg b/tcl/target/at91sam3u1e.cfg
index 47c227b..dc5c82c 100644
--- a/tcl/target/at91sam3u1e.cfg
+++ b/tcl/target/at91sam3u1e.cfg
@@ -4,5 +4,3 @@ source [find target/at91sam3uxx.cfg]
 # size is automatically "calculated" by probing
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
-
-
diff --git a/tcl/target/at91sam3u2c.cfg b/tcl/target/at91sam3u2c.cfg
index 47c227b..dc5c82c 100644
--- a/tcl/target/at91sam3u2c.cfg
+++ b/tcl/target/at91sam3u2c.cfg
@@ -4,5 +4,3 @@ source [find target/at91sam3uxx.cfg]
 # size is automatically "calculated" by probing
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
-
-
diff --git a/tcl/target/at91sam3u2e.cfg b/tcl/target/at91sam3u2e.cfg
index 47c227b..dc5c82c 100644
--- a/tcl/target/at91sam3u2e.cfg
+++ b/tcl/target/at91sam3u2e.cfg
@@ -4,5 +4,3 @@ source [find target/at91sam3uxx.cfg]
 # size is automatically "calculated" by probing
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
-
-
diff --git a/tcl/target/at91sam3u4c.cfg b/tcl/target/at91sam3u4c.cfg
index 5cacbcb..14af008 100644
--- a/tcl/target/at91sam3u4c.cfg
+++ b/tcl/target/at91sam3u4c.cfg
@@ -7,5 +7,3 @@ flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
 # This is a 256K chip, it has the 2nd bank
 set _FLASHNAME $_CHIPNAME.flash1
 flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
-
-
diff --git a/tcl/target/at91sam3u4e.cfg b/tcl/target/at91sam3u4e.cfg
index a48f992..fbe2dd9 100644
--- a/tcl/target/at91sam3u4e.cfg
+++ b/tcl/target/at91sam3u4e.cfg
@@ -7,5 +7,3 @@ flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
 # This is a 256K chip - it has the 2nd bank
 set _FLASHNAME $_CHIPNAME.flash1
 flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
-
-
diff --git a/tcl/target/at91sam3uxx.cfg b/tcl/target/at91sam3uxx.cfg
index b42ae19..5b1748b 100644
--- a/tcl/target/at91sam3uxx.cfg
+++ b/tcl/target/at91sam3uxx.cfg
@@ -8,4 +8,3 @@
 # at91sam3u1c
 
 source [find target/at91sam3XXX.cfg]
-
diff --git a/tcl/target/at91sam4XXX.cfg b/tcl/target/at91sam4XXX.cfg
index ff73670..ebb7eed 100644
--- a/tcl/target/at91sam4XXX.cfg
+++ b/tcl/target/at91sam4XXX.cfg
@@ -50,9 +50,9 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
 
-adapter_khz 500
+adapter speed 500
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
diff --git a/tcl/target/at91sam4lXX.cfg b/tcl/target/at91sam4lXX.cfg
index 4aee7d0..b73babc 100644
--- a/tcl/target/at91sam4lXX.cfg
+++ b/tcl/target/at91sam4lXX.cfg
@@ -21,7 +21,7 @@ reset_config srst_gates_jtag
 # Datasheet does not specify SYSCLK to JTAG/SWD clock ratio.
 # Usually used SYSCLK/6 is hell slow, testing shows that debugging can work @ SYSCLK/2
 # but your mileage may vary.
-adapter_khz 50
+adapter speed 50
 
 # System RC oscillator RCSYS starts in 3 cycles
-adapter_nsrst_delay 0
+adapter srst delay 0
diff --git a/tcl/target/at91sam7se512.cfg b/tcl/target/at91sam7se512.cfg
index ab09701..61b4781 100644
--- a/tcl/target/at91sam7se512.cfg
+++ b/tcl/target/at91sam7se512.cfg
@@ -36,4 +36,3 @@ $_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-a
 #flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
-
diff --git a/tcl/target/at91sam9.cfg b/tcl/target/at91sam9.cfg
index bf99fb2..e0ea316 100644
--- a/tcl/target/at91sam9.cfg
+++ b/tcl/target/at91sam9.cfg
@@ -24,10 +24,10 @@ reset_config trst_and_srst separate trst_push_pull srst_open_drain
 
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-adapter_nsrst_delay 300
+adapter srst delay 300
 jtag_ntrst_delay 200
 
-adapter_khz 3
+adapter speed 3
 
 ######################
 # Target configuration
diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
index 9ab7409..3e4b7d7 100644
--- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
+++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
@@ -6,15 +6,15 @@ source [find target/at91sam9261.cfg]
 
 reset_config trst_and_srst
 
-adapter_khz 4
+adapter speed 4
 
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
 
 scan_chain
 $_TARGETNAME configure -event reset-start {
 	# at reset chip runs at 32khz
-	adapter_khz 8
+	adapter speed 8
 }
 
 $_TARGETNAME configure -event reset-init {at91sam_init}
@@ -46,7 +46,7 @@ proc at91sam_init { } {
 	sleep 10                          ;# wait 10 ms
 
 	# Now run at anything fast... ie: 10mhz!
-	adapter_khz 10000                    ;# Increase JTAG Speed to 6 MHz
+	adapter speed 10000               ;# Increase JTAG Speed to 6 MHz
 
 	mww 0xffffec00 0x0a0a0a0a         ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
 	mww 0xffffec04 0x0b0b0b0b         ;# SMC_PULSE0
diff --git a/tcl/target/at91sam9g20.cfg b/tcl/target/at91sam9g20.cfg
index 3f5e3c6..6e45df2 100644
--- a/tcl/target/at91sam9g20.cfg
+++ b/tcl/target/at91sam9g20.cfg
@@ -12,7 +12,7 @@ source [find target/at91sam9.cfg]
 
 # Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
 
-adapter_khz 5
+adapter speed 5
 
 # Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
 # AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
diff --git a/tcl/target/at91samdXX.cfg b/tcl/target/at91samdXX.cfg
index f0644d1..9a396fa 100644
--- a/tcl/target/at91samdXX.cfg
+++ b/tcl/target/at91samdXX.cfg
@@ -66,12 +66,12 @@ reset_config srst_gates_jtag
 # This limit is most probably imposed by incorrectly handled SWD WAIT
 # on some SWD adapters.
 
-adapter_khz 400
+adapter speed 400
 
 # Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
 # without problem at maximal clock speed. Atmel recommends
 # adapter speed less than 10 * CPU clock.
-# adapter_khz 5000
+# adapter speed 5000
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/atheros_ar9331.cfg b/tcl/target/atheros_ar9331.cfg
index bea37ed..6ab238c 100644
--- a/tcl/target/atheros_ar9331.cfg
+++ b/tcl/target/atheros_ar9331.cfg
@@ -41,12 +41,12 @@ reset_config none srst_pulls_trst
 # For SRST based variant we still need proper timings.
 # For ETH part the reset should be asserted at least for 10ms
 # Since there is no other information let's take 100ms to be sure.
-adapter_nsrst_assert_width 100
+adapter srst pulse_width 100
 
 # according to the SoC documentation it should take at least 5ms from
 # reset end till bootstrap end. In the practice we need 8ms to get JTAG back
 # to live.
-adapter_nsrst_delay 8
+adapter srst delay 8
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $_CHIPNAME
diff --git a/tcl/target/atmega128.cfg b/tcl/target/atmega128.cfg
index b8f7d01..07161d5 100644
--- a/tcl/target/atmega128.cfg
+++ b/tcl/target/atmega128.cfg
@@ -4,10 +4,10 @@
    set _ENDIAN little
 
 # jtag speed
-adapter_khz 4500
+adapter speed 4500
 
 reset_config srst_only
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 #jtag scan chain
 if { [info exists CPUTAPID] } {
@@ -27,7 +27,7 @@ flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME
 
 #to use it, script will be like:
 #init
-#adapter_khz 4500
+#adapter speed 4500
 #reset init
 #verify_ircapture disable
 #
diff --git a/tcl/target/atmega128rfa1.cfg b/tcl/target/atmega128rfa1.cfg
index 2c12a61..cda439d 100644
--- a/tcl/target/atmega128rfa1.cfg
+++ b/tcl/target/atmega128rfa1.cfg
@@ -2,7 +2,7 @@ set _CHIPNAME avr
 set _ENDIAN little
 
 # jtag speed
-adapter_khz 4500
+adapter speed 4500
 
 # avr jtag docs never connect RSTN
 reset_config none
diff --git a/tcl/target/atsame5x.cfg b/tcl/target/atsame5x.cfg
index 61949cf..351a2ca 100644
--- a/tcl/target/atsame5x.cfg
+++ b/tcl/target/atsame5x.cfg
@@ -63,7 +63,7 @@ reset_config srst_gates_jtag
 # Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
 # without problem at clock speed over 5000 khz. Atmel recommends
 # adapter speed less than 10 * CPU clock.
-adapter_khz 2000
+adapter speed 2000
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/atsamv.cfg b/tcl/target/atsamv.cfg
index 43962de..fdd8354 100644
--- a/tcl/target/atsamv.cfg
+++ b/tcl/target/atsamv.cfg
@@ -39,7 +39,7 @@ target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
-adapter_khz 1800
+adapter speed 1800
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
@@ -57,4 +57,3 @@ if {![using_hla]} {
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
-
diff --git a/tcl/target/avr32.cfg b/tcl/target/avr32.cfg
index f5ee1a4..8295f5e 100644
--- a/tcl/target/avr32.cfg
+++ b/tcl/target/avr32.cfg
@@ -3,7 +3,7 @@ set _ENDIAN big
 
 set _CPUTAPID 0x21e8203f
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 reset_config trst_and_srst separate
@@ -14,4 +14,3 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_CP
 
 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
 target create $_TARGETNAME avr32_ap7k -endian $_ENDIAN -chain-position $_TARGETNAME
-
diff --git a/tcl/target/bcm6348.cfg b/tcl/target/bcm6348.cfg
index 2540b51..a9be559 100644
--- a/tcl/target/bcm6348.cfg
+++ b/tcl/target/bcm6348.cfg
@@ -1,7 +1,7 @@
 set _CHIPNAME bcm6348
 set _CPUID 0x0634817f
 
-adapter_khz 1000
+adapter speed 1000
 
 jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID
 
diff --git a/tcl/target/bluefield.cfg b/tcl/target/bluefield.cfg
new file mode 100644
index 0000000..b31dfe8
--- /dev/null
+++ b/tcl/target/bluefield.cfg
@@ -0,0 +1,78 @@
+# BlueField SoC Target
+
+set _CHIPNAME bluefield
+
+# Specify the target device
+#rshim device /dev/rshim0/rshim
+
+# Main DAP
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x4ba00477
+}
+
+adapter speed 1500
+
+swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# Initialize the target name and command variable.
+set _TARGETNAME $_CHIPNAME.cpu
+set _smp_command ""
+
+# CTI relative address
+set $_TARGETNAME.cti(0) 0xC4020000
+set $_TARGETNAME.cti(1) 0xC4120000
+set $_TARGETNAME.cti(2) 0xC8020000
+set $_TARGETNAME.cti(3) 0xC8120000
+set $_TARGETNAME.cti(4) 0xCC020000
+set $_TARGETNAME.cti(5) 0xCC120000
+set $_TARGETNAME.cti(6) 0xD0020000
+set $_TARGETNAME.cti(7) 0xD0120000
+set $_TARGETNAME.cti(8) 0xD4020000
+set $_TARGETNAME.cti(9) 0xD4120000
+set $_TARGETNAME.cti(10) 0xD8020000
+set $_TARGETNAME.cti(11) 0xD8120000
+set $_TARGETNAME.cti(12) 0xDC020000
+set $_TARGETNAME.cti(13) 0xDC120000
+set $_TARGETNAME.cti(14) 0xE0020000
+set $_TARGETNAME.cti(15) 0xE0120000
+
+# Create debug targets for a number of cores starting from core '_core_start'.
+# Adjust the numbers according to board configuration.
+set _core_start 0
+set _cores 16
+
+# Create each core
+for { set _core $_core_start } { $_core < $_core_start + $_cores } { incr _core 1 } {
+    cti create cti$_core -dap $_CHIPNAME.dap -ctibase [set $_TARGETNAME.cti($_core)] -ap-num 0
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core"
+
+    if { $_core != $_core_start } {
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+    } else {
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+# Configure SMP
+if { $_cores > 1 } {
+    eval $_smp_command
+}
+
+# Make sure the default target is the boot core
+targets ${_TARGETNAME}0
+
+proc core_up { args } {
+	global _TARGETNAME
+
+	# Examine remaining cores
+	foreach _core [set args] {
+		${_TARGETNAME}$_core arp_examine
+	}
+}
diff --git a/tcl/target/bluenrg-x.cfg b/tcl/target/bluenrg-x.cfg
index b0dd61a..a9d321e 100644
--- a/tcl/target/bluenrg-x.cfg
+++ b/tcl/target/bluenrg-x.cfg
@@ -1,8 +1,9 @@
 #
-# bluenrg-1/2 devices support only SWD transports.
+# bluenrg-1/2 and bluenrg-lp devices support only SWD transports.
 #
 
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -20,15 +21,9 @@ if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE 0x5F00
 }
 
-adapter_khz 4000
+adapter speed 4000
 
-if { [info exists CPUTAPID] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   set _CPUTAPID 0x0bb11477
-}
-
-swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -expected-id 0x0bb11477 -expected-id 0x0bc11477
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
@@ -53,22 +48,27 @@ if {![using_hla]} {
 }
 
 $_TARGETNAME configure -event halted {
-	global WDOG_VALUE
-	global WDOG_VALUE_SET
-	# Stop watchdog during halt, if enabled
-	mem2array value 32 0x40700008 1
-	set WDOG_VALUE [expr ($value(0))]
-	if [expr ($value(0) & (1 << 1))] {
-		set WDOG_VALUE_SET 1
-		mww 0x40700008 [expr ($value(0) & 0xFFFFFFFD)]
-	}
+    global WDOG_VALUE
+    global WDOG_VALUE_SET
+    set _JTAG_IDCODE [mrw 0x40000004]
+    if {$_JTAG_IDCODE != 0x0201E041} {
+        # Stop watchdog during halt, if enabled. Only Bluenrg-1/2
+        set WDOG_VALUE [mrw 0x40700008]
+        if [expr ($WDOG_VALUE & (1 << 1))] {
+            set WDOG_VALUE_SET 1
+            mww 0x40700008 [expr ($WDOG_VALUE & 0xFFFFFFFD)]
+        }
+    }
 }
 $_TARGETNAME configure -event resumed {
-	global WDOG_VALUE
-	global WDOG_VALUE_SET
-	if [expr $WDOG_VALUE_SET] {
-		# Restore watchdog enable value after resume
-		mww 0x40700008 $WDOG_VALUE
-		set WDOG_VALUE_SET 0
-       }
+    global WDOG_VALUE
+    global WDOG_VALUE_SET
+    set _JTAG_IDCODE [mrw 0x40000004]
+    if {$_JTAG_IDCODE != 0x0201E041} {
+        if [expr $WDOG_VALUE_SET] {
+            # Restore watchdog enable value after resume. Only Bluenrg-1/2
+            mww 0x40700008 $WDOG_VALUE
+            set WDOG_VALUE_SET 0
+           }
+   }
 }
diff --git a/tcl/target/c100.cfg b/tcl/target/c100.cfg
index 1eaa8fe..5b4354e 100644
--- a/tcl/target/c100.cfg
+++ b/tcl/target/c100.cfg
@@ -3,7 +3,7 @@
 # this script only configures one core (that is used to run Linux)
 
 # assume no PLL lock, start slowly
-adapter_khz 100
+adapter speed 100
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/c100config.tcl b/tcl/target/c100config.tcl
index 52efa83..53b2c5d 100644
--- a/tcl/target/c100config.tcl
+++ b/tcl/target/c100config.tcl
@@ -1,5 +1,5 @@
 
-# board(-config) specfic parameters file.
+# board(-config) specific parameters file.
 
 # set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
 proc config {label} {
@@ -409,4 +409,4 @@ proc flashUBOOT {file} {
     putsUART0 "done.\n"
     putsUART0 "Rebooting, please wait!\n"
     reboot
-}
\ No newline at end of file
+}
diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl
index c9124cb..725ba70 100644
--- a/tcl/target/c100helper.tcl
+++ b/tcl/target/c100helper.tcl
@@ -15,7 +15,7 @@ proc helpC100 {} {
     echo "12) ooma_board_detect: will show which version of Telo you have"
     echo "13) setupDDR2:         will configure DDR2 controller, you must have PLLs configureg"
     echo "14) showDDR2:          will show DDR2 config registers"
-    echo "15) showWatchdog:      will show current regster config for watchdog"
+    echo "15) showWatchdog:      will show current register config for watchdog"
     echo "16) reboot:            will trigger watchdog and reboot Telo (hw reset)"
     echo "17) bootNOR:           will boot Telo from NOR"
     echo "18) setupUART0:        will configure UART0 for 115200 8N1, PLLs have to be confiured"
@@ -176,7 +176,7 @@ proc setupAmbaClk {} {
     mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
     mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
     # wait for PLL to lock
-    echo "Wating for Amba PLL to lock"
+    echo "Waiting for Amba PLL to lock"
     while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 }
     # remove the internal PLL bypass
     mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
@@ -250,7 +250,7 @@ proc setupArmClk {} {
     mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
     mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
     # wait for PLL to lock
-    echo "Wating for Amba PLL to lock"
+    echo "Waiting for Amba PLL to lock"
     while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 }
     # remove the internal PLL bypass
     mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
@@ -300,7 +300,7 @@ proc setupDDR2 {} {
 
     # Memory setup register
     mww $MEMORY_MAX_ADDR  [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR]
-    # disbale ROM remap
+    # disable ROM remap
     mww $MEMORY_CR 0x0
     # Take DDR controller out of reset
     mmw $BLOCK_RESET_REG $DDR_RST 0x0
@@ -486,15 +486,15 @@ proc reboot {} {
     set TIMER_WDT_CURRENT_COUNT	[regs TIMER_WDT_CURRENT_COUNT]
 
     # allow the counter to count to high value  before triggering
-    # this is because regsiter writes are slow over JTAG and
+    # this is because register writes are slow over JTAG and
     # I don't want to miss the high_bound==curr_count condition
     mww $TIMER_WDT_HIGH_BOUND  0xffffff
     mww $TIMER_WDT_CURRENT_COUNT 0x0
     echo "JTAG speed lowered to 100kHz"
-    adapter_khz 100
+    adapter speed 100
     mww $TIMER_WDT_CONTROL 0x1
     # wait until the reset
-    echo -n "Wating for watchdog to trigger..."
+    echo -n "Waiting for watchdog to trigger..."
     #while {[mrw $TIMER_WDT_CONTROL] == 1} {
     #    echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
     #    sleep 1
diff --git a/tcl/target/cc2538.cfg b/tcl/target/cc2538.cfg
index 63fd9c2..8d232f4 100755..100644
--- a/tcl/target/cc2538.cfg
+++ b/tcl/target/cc2538.cfg
@@ -1,7 +1,7 @@
 # Config for Texas Instruments low power RF SoC CC2538
 # http://www.ti.com/lit/pdf/swru319
 
-adapter_khz 100
+adapter speed 100
 
 source [find target/icepick.cfg]
 source [find target/ti-cjtag.cfg]
diff --git a/tcl/target/cs351x.cfg b/tcl/target/cs351x.cfg
index cb05da2..8fabda6 100644
--- a/tcl/target/cs351x.cfg
+++ b/tcl/target/cs351x.cfg
@@ -28,4 +28,3 @@ target create $_TARGETNAME fa526 -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # This chip has a DCC ... use it
 arm7_9 dcc_downloads enable
-
diff --git a/tcl/target/dragonite.cfg b/tcl/target/dragonite.cfg
index 750fd64..b9d73a2 100644
--- a/tcl/target/dragonite.cfg
+++ b/tcl/target/dragonite.cfg
@@ -26,6 +26,5 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME dragonite -endian $_ENDIAN -chain-position $_TARGETNAME
 
 reset_config trst_and_srst
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
-
diff --git a/tcl/target/dsp56321.cfg b/tcl/target/dsp56321.cfg
index 6f32223..78ecb3b 100644
--- a/tcl/target/dsp56321.cfg
+++ b/tcl/target/dsp56321.cfg
@@ -1,13 +1,13 @@
 # Script for freescale DSP56321
 #
 
-if { [info exists CHIPNAME] } {	
+if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
    set _CHIPNAME dsp56321
 }
 
-if { [info exists ENDIAN] } {	
+if { [info exists ENDIAN] } {
    set _ENDIAN $ENDIAN
 } else {
   # this defaults to a big endian
@@ -21,7 +21,7 @@ if { [info exists CPUTAPID] } {
 }
 
 #jtag speed
-adapter_khz 4500
+adapter speed 4500
 
 #has only srst
 reset_config srst_only
diff --git a/tcl/target/dsp568013.cfg b/tcl/target/dsp568013.cfg
index 0c491fa..67d4419 100644
--- a/tcl/target/dsp568013.cfg
+++ b/tcl/target/dsp568013.cfg
@@ -1,12 +1,12 @@
 # Script for freescale DSP568013
 
-if { [info exists CHIPNAME] } {	
+if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
    set _CHIPNAME dsp568013
 }
 
-if { [info exists ENDIAN] } {	
+if { [info exists ENDIAN] } {
    set _ENDIAN $ENDIAN
 } else {
   # this defaults to a big endian
@@ -20,7 +20,7 @@ if { [info exists CPUTAPID] } {
 }
 
 #jtag speed
-adapter_khz 800
+adapter speed 800
 
 reset_config srst_only
 
@@ -35,7 +35,7 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # Setup the interesting tap
-# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations requiere certain instruction to be in the IR register during reset, and polling would change this)
+# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations require certain instruction to be in the IR register during reset, and polling would change this)
 jtag configure $_CHIPNAME.chp -event setup "
      jtag tapenable $_TARGETNAME
      poll off
@@ -73,4 +73,3 @@ $_TARGETNAME configure -work-area-virt 0
 #setup flash
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME
-
diff --git a/tcl/target/dsp568037.cfg b/tcl/target/dsp568037.cfg
index 01194d0..fc57bd4 100644
--- a/tcl/target/dsp568037.cfg
+++ b/tcl/target/dsp568037.cfg
@@ -20,7 +20,7 @@ if { [info exists CPUTAPID] } {
 }
 
 #jtag speed
-adapter_khz 800
+adapter speed 800
 
 reset_config srst_only
 
@@ -69,4 +69,3 @@ $_TARGETNAME configure -work-area-virt 0
 #setup flash
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME
-
diff --git a/tcl/target/efm32.cfg b/tcl/target/efm32.cfg
index e22ce5c..c789efc 100644
--- a/tcl/target/efm32.cfg
+++ b/tcl/target/efm32.cfg
@@ -34,7 +34,7 @@ if { [info exists CPUTAPID] } {
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
-adapter_khz 1000
+adapter speed 1000
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
diff --git a/tcl/target/epc9301.cfg b/tcl/target/epc9301.cfg
index f186d37..252bbab 100644
--- a/tcl/target/epc9301.cfg
+++ b/tcl/target/epc9301.cfg
@@ -20,7 +20,7 @@ if { [info exists CPUTAPID] } {
 }
 
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 set _TARGETNAME $_CHIPNAME.cpu
diff --git a/tcl/target/esi32xx.cfg b/tcl/target/esi32xx.cfg
index d32af39..6be84ab 100644
--- a/tcl/target/esi32xx.cfg
+++ b/tcl/target/esi32xx.cfg
@@ -26,7 +26,7 @@ if { [info exists CACHEARCH] } {
     $_TARGETNAME esirisc cache_arch $CACHEARCH
 }
 
-adapter_khz 2000
+adapter speed 2000
 
 reset_config none
 
diff --git a/tcl/target/feroceon.cfg b/tcl/target/feroceon.cfg
index 389576e..d4f710e 100644
--- a/tcl/target/feroceon.cfg
+++ b/tcl/target/feroceon.cfg
@@ -26,6 +26,5 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME
 
 reset_config trst_and_srst
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
-
diff --git a/tcl/target/fm3.cfg b/tcl/target/fm3.cfg
index a0610ce..544cff9 100644
--- a/tcl/target/fm3.cfg
+++ b/tcl/target/fm3.cfg
@@ -22,7 +22,7 @@ if { [info exists CPUTAPID] } {
 }
 
 # delays on reset lines
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
    jtag_ntrst_delay 100
 }
@@ -36,16 +36,16 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
-# MB9BF506 has 64kB of SRAM on its main system bus 
+# MB9BF506 has 64kB of SRAM on its main system bus
 $_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
 
-# MB9BF506 has 512kB internal FLASH 
+# MB9BF506 has 512kB internal FLASH
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
 
 # 4MHz / 6 = 666kHz, so use 500
-adapter_khz 500
+adapter speed 500
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/fm4.cfg b/tcl/target/fm4.cfg
index b79634d..bfe7115 100644
--- a/tcl/target/fm4.cfg
+++ b/tcl/target/fm4.cfg
@@ -24,7 +24,7 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
 
-adapter_khz 500
+adapter speed 500
 
 if {![using_hla]} {
 	cortex_m reset_config sysresetreq
diff --git a/tcl/target/gp326xxxa.cfg b/tcl/target/gp326xxxa.cfg
index feb7554..df42c44 100644
--- a/tcl/target/gp326xxxa.cfg
+++ b/tcl/target/gp326xxxa.cfg
@@ -33,11 +33,11 @@ $_TARGETNAME configure -work-area-phys 0xf8000000 -work-area-size 0x8000 -work-a
 reset_config trst_and_srst srst_pulls_trst
 # This delay is needed otherwise communication with the target would
 # be unreliable
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 # Set the adapter speed ridiculously low just in case we are
 # running off of a 32kHz clock
-adapter_khz 2
+adapter speed 2
 
 proc gp32xxxa_halt_and_reset_control_registers {} {
 	# System control registers
@@ -57,7 +57,7 @@ proc gp32xxxa_halt_and_reset_control_registers {} {
 
 	# Set the adapter speed ridiculously low just in case we are
 	# running off of a 32kHz clock
-	adapter_khz 2
+	adapter speed 2
 
 	# Disable any advanced features at this stage
 	arm7_9 dcc_downloads disable
@@ -86,7 +86,7 @@ proc gp32xxxa_halt_and_reset_control_registers {} {
 
 	# Now that we know that we are running at 48Mhz
 	# Increase JTAG speed and enable speed optimization features
-	adapter_khz 5000
+	adapter speed 5000
 	arm7_9 dcc_downloads enable
 	arm7_9 fast_memory_access enable
 }
diff --git a/tcl/target/hilscher_netx10.cfg b/tcl/target/hilscher_netx10.cfg
index 3f96607..668de8f 100644
--- a/tcl/target/hilscher_netx10.cfg
+++ b/tcl/target/hilscher_netx10.cfg
@@ -28,4 +28,3 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
 # that TAP is associated with a target
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
-
diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg
index a945bea..d125071 100644
--- a/tcl/target/icepick.cfg
+++ b/tcl/target/icepick.cfg
@@ -75,9 +75,22 @@ proc icepick_c_setup {jrc} {
 }
 
 # jrc	== TAP name for the ICEpick
-# port	== a port number, 0..15
+# port	== a port number, 0..15 for debug tap, 16..31 for test tap
 proc icepick_c_tapenable {jrc port} {
 
+	if { ($port >= 0) && ($port < 16) } {
+		# Debug tap"
+		set tap $port
+		set block 0x2
+	} elseif { $port < 32 } {
+		# Test tap
+		set tap [expr ($port - 16)]
+		set block 0x1
+	} else {
+		echo "ERROR: Invalid ICEPick C port number: $port"
+		return
+	}
+
 	# First CONNECT to the ICEPick
 #	echo "Connecting to ICEPick"
 	icepick_c_connect $jrc
@@ -90,18 +103,18 @@ proc icepick_c_tapenable {jrc port} {
 	# And never to enter RESET, which will disable the TAPs.
 
 	# first enable power and clock for TAP
-	icepick_c_router $jrc 1 0x2 $port 0x110048
+	icepick_c_router $jrc 1 $block $tap 0x110048
 
 	# TRM states that the register should be read back here, skipped for now
 
 	# enable debug "default" mode
-	icepick_c_router $jrc 1 0x2 $port 0x112048
+	icepick_c_router $jrc 1 $block $tap 0x112048
 
 	# TRM states that debug enable and debug mode should be read back and
 	# confirmed - skipped for now
 
 	# Finally select the tap
-	icepick_c_router $jrc 1 0x2 $port 0x112148
+	icepick_c_router $jrc 1 $block $tap 0x112148
 
 	# Enter the bypass state
 	irscan $jrc [CONST IR_BYPASS] -endstate RUN/IDLE
@@ -119,6 +132,7 @@ proc icepick_d_set_core_control {jrc coreid value } {
 # Follow the sequence described in
 # http://processors.wiki.ti.com/images/f/f6/Router_Scan_Sequence-ICEpick-D.pdf
 proc icepick_d_tapenable {jrc port coreid { value 0x2008 } } {
+
 	# First CONNECT to the ICEPick
 	icepick_c_connect $jrc
 	icepick_c_setup $jrc
@@ -140,4 +154,3 @@ proc icepick_c_wreset {jrc} {
 	# send a router write, block is 0, register is 1, value is 0x2100
 	icepick_c_router $jrc 1 0x0 0x1 0x002101
 }
-
diff --git a/tcl/target/imx.cfg b/tcl/target/imx.cfg
index 9eea53e..ccfddb6 100644
--- a/tcl/target/imx.cfg
+++ b/tcl/target/imx.cfg
@@ -6,7 +6,7 @@ set TARGETNAME $_TARGETNAME
 # rewrite commands of the form below to arm11 mcr...
 #	Data.Set c15:0x042f %long 0x40000015
 proc setc15 {regs value} {
-	global TARGETNAME 
+	global TARGETNAME
 
 	echo [format "set p15 0x%04x, 0x%08x" $regs $value]
 
diff --git a/tcl/target/imx28.cfg b/tcl/target/imx28.cfg
index 4cc3950..1fea3fa 100644
--- a/tcl/target/imx28.cfg
+++ b/tcl/target/imx28.cfg
@@ -4,7 +4,7 @@
 reset_config trst_and_srst
 
 #jtag nTRST and nSRST delay
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 if { [info exists CHIPNAME] } {
diff --git a/tcl/target/imx31.cfg b/tcl/target/imx31.cfg
index ca63951..d850657 100644
--- a/tcl/target/imx31.cfg
+++ b/tcl/target/imx31.cfg
@@ -3,7 +3,7 @@
 
 reset_config trst_and_srst srst_gates_jtag
 
-adapter_nsrst_delay 5
+adapter srst delay 5
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg
index f359346..2945334 100644
--- a/tcl/target/imx6.cfg
+++ b/tcl/target/imx6.cfg
@@ -75,7 +75,7 @@ proc imx6_dbginit {target} {
 }
 
 # Slow speed to be sure it will work
-adapter_khz 1000
-$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
+adapter speed 1000
+$_TARGETNAME configure -event reset-start { adapter speed 1000 }
 
 $_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
diff --git a/tcl/target/infineon/tle987x.cfg b/tcl/target/infineon/tle987x.cfg
new file mode 100644
index 0000000..84cc238
--- /dev/null
+++ b/tcl/target/infineon/tle987x.cfg
@@ -0,0 +1,36 @@
+#
+# Infineon TLE987x family (Arm Cortex-M3 @ up to 40 MHz)
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME tle987x
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CPU_SWD_TAPID] } {
+	set _CPU_SWD_TAPID $CPU_SWD_TAPID
+} else {
+	set _CPU_SWD_TAPID 0x2BA01477
+}
+
+if { [using_jtag] } {
+	# JTAG not supported, only SWD
+	set _CPU_TAPID 0
+} else {
+	set _CPU_TAPID $_CPU_SWD_TAPID
+}
+
+swj_newdap $_CHIPNAME dap -irlen 4 -expected-id $_CPU_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+if { ![using_hla] } {
+	cortex_m reset_config sysresetreq
+}
+
+adapter speed 1000
diff --git a/tcl/target/is5114.cfg b/tcl/target/is5114.cfg
index 31f1aa1..1a06b09 100644
--- a/tcl/target/is5114.cfg
+++ b/tcl/target/is5114.cfg
@@ -23,7 +23,7 @@ if { [info exists CPUTAPID] } {
 }
 
 # jtag speed. We need to stick to 16kHz until we've finished reset.
-adapter_khz 16
+adapter speed 16
 
 reset_config trst_and_srst
 
@@ -38,9 +38,9 @@ jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
 
-$_TARGETNAME configure -event reset-start { adapter_khz 16 }
+$_TARGETNAME configure -event reset-start { adapter speed 16 }
 $_TARGETNAME configure -event reset-init {
 	# We can increase speed now that we know the target is halted.
-	adapter_khz 3000
+	adapter speed 3000
 }
 $_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1
diff --git a/tcl/target/ixp42x.cfg b/tcl/target/ixp42x.cfg
index d7b5bf4..624fe29 100644
--- a/tcl/target/ixp42x.cfg
+++ b/tcl/target/ixp42x.cfg
@@ -66,8 +66,8 @@ set IXP42x_SDRAM_256MB_32Mx16_2BANK	0x0015
 
 # helper function to init SDRAM on IXP42x.
 # SDRAM_CFG: one of IXP42X_SDRAM_xxx
-# REFRESH: refresh counter reload value (integer) 
-# CASLAT: 2 or 3 
+# REFRESH: refresh counter reload value (integer)
+# CASLAT: 2 or 3
 proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {
 
     switch $CASLAT {
@@ -104,4 +104,3 @@ proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {
 proc ixp42x_set_bigendian { } {
     reg XSCALE_CTRL 0xF8
 }
-
diff --git a/tcl/target/k1921vk01t.cfg b/tcl/target/k1921vk01t.cfg
index 1a84021..926f3c7 100755..100644
--- a/tcl/target/k1921vk01t.cfg
+++ b/tcl/target/k1921vk01t.cfg
@@ -40,9 +40,9 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 
 flash bank $_CHIPNAME.flash niietcm4 0 0 0 0 $_TARGETNAME
 
-adapter_khz 2000
+adapter speed 2000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
    jtag_ntrst_delay 100
 }
diff --git a/tcl/target/ke0x.cfg b/tcl/target/ke0x.cfg
index 8239400..b92721f 100644
--- a/tcl/target/ke0x.cfg
+++ b/tcl/target/ke0x.cfg
@@ -35,7 +35,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
 
-adapter_khz 1000
+adapter speed 1000
 
 reset_config srst_nogate
 
diff --git a/tcl/target/klx.cfg b/tcl/target/klx.cfg
index 5d9286a..84f6535 100644
--- a/tcl/target/klx.cfg
+++ b/tcl/target/klx.cfg
@@ -40,7 +40,7 @@ kinetis create_banks
 # Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual
 # specifies up to 1MHz for VLPR mode and up to 24MHz for run mode;
 # Table 17 of Sub-Family Data Sheet rev4 lists 25MHz as the maximum frequency.
-adapter_khz 1000
+adapter speed 1000
 
 reset_config srst_nogate
 
@@ -56,9 +56,9 @@ if {[using_hla]} {
    echo " it without mass erase. Don't set write protection on the first block."
    echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
    echo ""
-} {
-   # Detect secured MCU or boot lock-up in RESET/WDOG loop
-   $_CHIPNAME.cpu configure -event examine-start {
+} else {
+   # Detect secured MCU
+   $_TARGETNAME configure -event examine-fail {
       kinetis mdm check_security
    }
 
diff --git a/tcl/target/ks869x.cfg b/tcl/target/ks869x.cfg
index 0f6829c..78cc402 100644
--- a/tcl/target/ks869x.cfg
+++ b/tcl/target/ks869x.cfg
@@ -18,7 +18,7 @@ if { [info exists CPUTAPID] } {
    set  _CPUTAPID 0x00922f0f
 }
 
-adapter_khz 6000
+adapter speed 6000
 
 # jtag scan chain
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
diff --git a/tcl/target/kx.cfg b/tcl/target/kx.cfg
index 73ee62a..9fda4ed 100644
--- a/tcl/target/kx.cfg
+++ b/tcl/target/kx.cfg
@@ -41,7 +41,7 @@ set _FLASHNAME $_CHIPNAME.pflash
 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
 kinetis create_banks
 
-adapter_khz 1000
+adapter speed 1000
 
 reset_config srst_nogate
 
@@ -58,9 +58,13 @@ if {[using_hla]} {
    echo " it without mass erase. Don't set write protection on the first block."
    echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
    echo ""
-} {
+} else {
    # Detect secured MCU or boot lock-up in RESET/WDOG loop
-   $_CHIPNAME.cpu configure -event examine-start {
+   $_TARGETNAME configure -event examine-fail {
+      kinetis mdm check_security
+   }
+   # During RESET/WDOG loop the target is sometimes falsely examined
+   $_TARGETNAME configure -event examine-end {
       kinetis mdm check_security
    }
 
@@ -75,4 +79,3 @@ if {[using_hla]} {
 $_TARGETNAME configure -event reset-init {
    kinetis disable_wdog
 }
-
diff --git a/tcl/target/lpc1850.cfg b/tcl/target/lpc1850.cfg
index 925a049..481dc8a 100644
--- a/tcl/target/lpc1850.cfg
+++ b/tcl/target/lpc1850.cfg
@@ -1,6 +1,6 @@
 source [find target/swj-dp.tcl]
 
-adapter_khz 500
+adapter speed 500
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/lpc1xxx.cfg b/tcl/target/lpc1xxx.cfg
index 1969e46..946d1ce 100644
--- a/tcl/target/lpc1xxx.cfg
+++ b/tcl/target/lpc1xxx.cfg
@@ -145,10 +145,10 @@ if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "l
 # Run with *real slow* clock by default since the
 # boot rom could have been playing with the PLL, so
 # we have no idea what clock the target is running at.
-adapter_khz 10
+adapter speed 10
 
 # delays on reset lines
-adapter_nsrst_delay 200
+adapter srst delay 200
 if {[using_jtag]} {
  jtag_ntrst_delay 200
 }
diff --git a/tcl/target/lpc2103.cfg b/tcl/target/lpc2103.cfg
index f55777f..131b9ef 100644
--- a/tcl/target/lpc2103.cfg
+++ b/tcl/target/lpc2103.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2103 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
 	# default to core clocked with 12MHz crystal
 	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
-	
+
 	# setup_lpc2103 <core_freq_khz> <adapter_freq_khz>
 	setup_lpc2103 12000 1500
 }
diff --git a/tcl/target/lpc2124.cfg b/tcl/target/lpc2124.cfg
index 0251738..ddbde22 100644
--- a/tcl/target/lpc2124.cfg
+++ b/tcl/target/lpc2124.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2124 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
 	# default to core clocked with 12MHz crystal
 	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
-	
+
 	# setup_lpc2124 <core_freq_khz> <adapter_freq_khz>
 	setup_lpc2124 12000 1500
 }
diff --git a/tcl/target/lpc2129.cfg b/tcl/target/lpc2129.cfg
index 2c33cde..a1c3fe7 100644
--- a/tcl/target/lpc2129.cfg
+++ b/tcl/target/lpc2129.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2129 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
 	# default to core clocked with 12MHz crystal
 	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
-	
+
 	# setup_lpc2129 <core_freq_khz> <adapter_freq_khz>
 	setup_lpc2129 12000 1500
 }
diff --git a/tcl/target/lpc2148.cfg b/tcl/target/lpc2148.cfg
index f3a2011..503a682 100644
--- a/tcl/target/lpc2148.cfg
+++ b/tcl/target/lpc2148.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2148 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
 	# default to core clocked with 12MHz crystal
 	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
-	
+
 	# setup_lpc2148 <core_freq_khz> <adapter_freq_khz>
 	setup_lpc2148 12000 1500
 }
diff --git a/tcl/target/lpc2294.cfg b/tcl/target/lpc2294.cfg
index 83d595d..1320cda 100644
--- a/tcl/target/lpc2294.cfg
+++ b/tcl/target/lpc2294.cfg
@@ -9,7 +9,7 @@ source [find target/lpc2xxx.cfg]
 proc setup_lpc2294 {core_freq_khz adapter_freq_khz} {
 	# 256kB flash and 16kB SRAM
 	# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
-	
+
 	# !! TAPID unknown !!
 	setup_lpc2xxx lpc2294 0xffffffff 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz
 }
@@ -17,7 +17,7 @@ proc setup_lpc2294 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
 	# default to core clocked with 12MHz crystal
 	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
-	
+
 	# setup_lpc2294 <core_freq_khz> <adapter_freq_khz>
 	setup_lpc2294 12000 1500
 }
diff --git a/tcl/target/lpc2378.cfg b/tcl/target/lpc2378.cfg
index 0b66b82..235456a 100644
--- a/tcl/target/lpc2378.cfg
+++ b/tcl/target/lpc2378.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2378 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
 	# default to core clocked with 4MHz internal oscillator
 	echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
-	
+
 	# setup_lpc2378 <core_freq_khz> <adapter_freq_khz>
 	setup_lpc2378 4000 500
 }
diff --git a/tcl/target/lpc2460.cfg b/tcl/target/lpc2460.cfg
index 69fdc4a..c229f6d 100644
--- a/tcl/target/lpc2460.cfg
+++ b/tcl/target/lpc2460.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2460 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
 	# default to core clocked with 4MHz internal oscillator
 	echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
-	
+
 	# setup_lpc2460 <core_freq_khz> <adapter_freq_khz>
 	setup_lpc2460 4000 500
 }
diff --git a/tcl/target/lpc2478.cfg b/tcl/target/lpc2478.cfg
index 48e5bdf..36b5c46 100644
--- a/tcl/target/lpc2478.cfg
+++ b/tcl/target/lpc2478.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2478 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
 	# default to core clocked with 4MHz internal oscillator
 	echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
-	
+
 	# setup_lpc2478 <core_freq_khz> <adapter_freq_khz>
 	setup_lpc2478 4000 500
 }
diff --git a/tcl/target/lpc2900.cfg b/tcl/target/lpc2900.cfg
index 5367787..523bc21 100644
--- a/tcl/target/lpc2900.cfg
+++ b/tcl/target/lpc2900.cfg
@@ -14,7 +14,7 @@ if { [info exists CPUTAPID] } {
 if { [info exists HAS_ETB] } {
 } else {
     # Set default (no ETB).
-    # Show a warning, because this should have been configured explicitely.
+    # Show a warning, because this should have been configured explicitly.
     set HAS_ETB 0
     # TODO: warning?
 }
diff --git a/tcl/target/lpc2xxx.cfg b/tcl/target/lpc2xxx.cfg
index 11f1c48..f947c1b 100644
--- a/tcl/target/lpc2xxx.cfg
+++ b/tcl/target/lpc2xxx.cfg
@@ -13,10 +13,10 @@ proc setup_lpc2xxx {chip_name cputapids flash_size flash_variant workarea_size c
 	reset_config trst_and_srst
 
 	# reset delays
-	adapter_nsrst_delay 100
+	adapter srst delay 100
 	jtag_ntrst_delay 100
 
-	adapter_khz $adapter_freq_khz
+	adapter speed $adapter_freq_khz
 
 	foreach i $cputapids {
 		append expected_ids "-expected-id " $i " "
@@ -40,5 +40,5 @@ proc setup_lpc2xxx {chip_name cputapids flash_size flash_variant workarea_size c
 proc init_targets {} {
 	# FIX!!! read out CPUTAPID here and choose right setup. In addition to the
 	# CPUTAPID some querying of the target would be required.
-	return -error "This is a generic LPC2xxx configuration file, use a specific target file." 
+	return -error "This is a generic LPC2xxx configuration file, use a specific target file."
 }
diff --git a/tcl/target/lpc3131.cfg b/tcl/target/lpc3131.cfg
index 27c1f67..89bbf02 100644
--- a/tcl/target/lpc3131.cfg
+++ b/tcl/target/lpc3131.cfg
@@ -22,7 +22,7 @@ if { [info exists CPUTAPID] } {
 }
 
 # Scan Tap
-# Wired to seperate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module 
+# Wired to separate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module
 # JTAGSEL pin must be 0 to activate, which reassigns arm tdo to a pass through.
 if { [info exists SJCTAPID] } {
    set _SJCTAPID $SJCTAPID
@@ -52,11 +52,11 @@ dict set lpc313x wdt			0x13002400
 # Target configuration
 ##################################################################
 
-adapter_nsrst_delay 1000
+adapter srst delay 1000
 jtag_ntrst_delay 0
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME 
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME invoke-event halted
 
diff --git a/tcl/target/lpc4350.cfg b/tcl/target/lpc4350.cfg
index 2b72884..0c6d0ff 100644
--- a/tcl/target/lpc4350.cfg
+++ b/tcl/target/lpc4350.cfg
@@ -1,6 +1,6 @@
 source [find target/swj-dp.tcl]
 
-adapter_khz 500
+adapter speed 500
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/lpc4370.cfg b/tcl/target/lpc4370.cfg
index 1374ef2..9db2b9e 100644
--- a/tcl/target/lpc4370.cfg
+++ b/tcl/target/lpc4370.cfg
@@ -2,7 +2,7 @@
 # NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each
 #
 
-adapter_khz 500
+adapter speed 500
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/lpc8nxx.cfg b/tcl/target/lpc8nxx.cfg
index b933290..1bc77b2 100644
--- a/tcl/target/lpc8nxx.cfg
+++ b/tcl/target/lpc8nxx.cfg
@@ -22,7 +22,7 @@ if {![using_hla]} {
 	# If srst is not fitted use SYSRESETREQ to  perform a soft reset
 	cortex_m reset_config sysresetreq
 }
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x1ff0 -work-area-backup 0
 
diff --git a/tcl/target/ls1012a.cfg b/tcl/target/ls1012a.cfg
index 9a9e684..19d3e58 100644
--- a/tcl/target/ls1012a.cfg
+++ b/tcl/target/ls1012a.cfg
@@ -32,4 +32,4 @@ target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -dbgbase 0x80410000 -cti
 
 target smp $_TARGETNAME
 
-adapter_khz 2000
+adapter speed 2000
diff --git a/tcl/target/max32620.cfg b/tcl/target/max32620.cfg
index 80cb25a..6187bb9 100644
--- a/tcl/target/max32620.cfg
+++ b/tcl/target/max32620.cfg
@@ -2,7 +2,7 @@
 # www.maximintegrated.com
 
 # adapter speed
-adapter_khz 4000
+adapter speed 4000
 
 # reset pin configuration
 reset_config srst_only
diff --git a/tcl/target/max32625.cfg b/tcl/target/max32625.cfg
index 7182b23..159b360 100644
--- a/tcl/target/max32625.cfg
+++ b/tcl/target/max32625.cfg
@@ -2,7 +2,7 @@
 # www.maximintegrated.com
 
 # adapter speed
-adapter_khz 4000
+adapter speed 4000
 
 # reset pin configuration
 reset_config srst_only
diff --git a/tcl/target/max3263x.cfg b/tcl/target/max3263x.cfg
index f23b0b6..fc7d11f 100644
--- a/tcl/target/max3263x.cfg
+++ b/tcl/target/max3263x.cfg
@@ -2,7 +2,7 @@
 # www.maximintegrated.com
 
 # adapter speed
-adapter_khz 4000
+adapter speed 4000
 
 # reset pin configuration
 reset_config srst_only
diff --git a/tcl/target/mc13224v.cfg b/tcl/target/mc13224v.cfg
index 27ac8c3..f756dd9 100644
--- a/tcl/target/mc13224v.cfg
+++ b/tcl/target/mc13224v.cfg
@@ -35,8 +35,8 @@ reset_config srst_only
 jtag_ntrst_delay 200
 
 # rclk hasn't been working well. This maybe the mc13224v or something else.
-#adapter_khz 2000
-adapter_khz 2000
+#adapter speed 2000
+adapter speed 2000
 
 ######################
 # Target configuration
diff --git a/tcl/target/mdr32f9q2i.cfg b/tcl/target/mdr32f9q2i.cfg
index 6748102..820d2dd 100644
--- a/tcl/target/mdr32f9q2i.cfg
+++ b/tcl/target/mdr32f9q2i.cfg
@@ -49,9 +49,9 @@ if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
 }
 
 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
    jtag_ntrst_delay 100
 }
diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg
index 4f24020..d51a50e 100644
--- a/tcl/target/nrf51.cfg
+++ b/tcl/target/nrf51.cfg
@@ -50,7 +50,7 @@ flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
 #  The chip should start up from internal 16Mhz RC, so setting adapter
 #  clock to 1Mhz should be OK
 #
-adapter_khz 1000
+adapter speed 1000
 
 proc enable_all_ram {} {
 	# nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg
index c29adbd..88f2c69 100644
--- a/tcl/target/nrf52.cfg
+++ b/tcl/target/nrf52.cfg
@@ -30,13 +30,86 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
-adapter_khz 1000
+adapter speed 1000
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
-if { ![using_hla] } {
+if { [using_hla] } {
+	echo ""
+	echo "nRF52 device has a CTRL-AP dedicated to recover the device from AP lock."
+	echo "A high level adapter (like a ST-Link) you are currently using cannot access"
+	echo "the CTRL-AP so 'nrf52_recover' command will not work."
+	echo "Do not enable UICR APPROTECT."
+	echo ""
+} else {
 	cortex_m reset_config sysresetreq
+
+	$_TARGETNAME configure -event examine-fail nrf52_check_ap_lock
 }
 
 flash bank $_CHIPNAME.flash nrf5 0x00000000 0 1 1 $_TARGETNAME
 flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 1 1 $_TARGETNAME
+
+# Test if MEM-AP is locked by UICR APPROTECT
+proc nrf52_check_ap_lock {} {
+	set dap [[target current] cget -dap]
+	set err [catch {set APPROTECTSTATUS [ocd_$dap apreg 1 0xc]}]
+	if {$err == 0 && $APPROTECTSTATUS != 1} {
+		echo "****** WARNING ******"
+		echo "nRF52 device has AP lock engaged (see UICR APPROTECT register)."
+		echo "Debug access is denied."
+		echo "Use 'nrf52_recover' to erase and unlock the device."
+		echo ""
+		poll off
+	}
+}
+
+# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #1)
+# http://www.ebyte.com produces modules with nRF52 locked by default,
+# use nrf52_recover to enable flashing and debug.
+proc nrf52_recover {} {
+	set target [target current]
+	set dap [$target cget -dap]
+
+	set IDR [ocd_$dap apreg 1 0xfc]
+	if {$IDR != 0x02880000} {
+		echo "Error: Cannot access nRF52 CTRL-AP!"
+		return
+	}
+
+	poll off
+
+	# Assert reset
+	$dap apreg 1 0 1
+
+	# Reset ERASEALLSTATUS event
+	$dap apreg 1 8 0
+
+	# Trigger ERASEALL task
+	$dap apreg 1 4 0
+	$dap apreg 1 4 1
+
+	for {set i 0} {1} {incr i} {
+		set ERASEALLSTATUS [ocd_$dap apreg 1 8]
+		if {$ERASEALLSTATUS == 1} {
+			echo "$target device has been successfully erased and unlocked."
+			break
+		}
+		if {$i >= 5} {
+			echo "Error: $target recovery failed."
+			break
+		}
+		sleep 100
+	}
+
+	# Deassert reset
+	$dap apreg 1 0 0
+
+	if {$ERASEALLSTATUS == 1} {
+		sleep 100
+		$target arp_examine
+		poll on
+	}
+}
+
+add_help_text nrf52_recover "Mass erase and unlock nRF52 device"
diff --git a/tcl/target/numicro.cfg b/tcl/target/numicro.cfg
index c42dfbc..73022df 100644
--- a/tcl/target/numicro.cfg
+++ b/tcl/target/numicro.cfg
@@ -48,7 +48,7 @@ set _FLASHNAME $_CHIPNAME.flash_config
 flash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME
 
 # set default SWCLK frequency
-adapter_khz 1000
+adapter speed 1000
 
 # set default srst setting "none"
 reset_config none
diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index 078d7f2..dcf7c51 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -63,8 +63,8 @@ proc omap3_dbginit {target} {
 # be absolutely certain the JTAG clock will work with the worst-case
 # 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
 # OK to speed up *after* PLL and clock tree setup.
-adapter_khz 1000
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1000 }
+adapter speed 1000
+$_TARGETNAME configure -event "reset-start" { adapter speed 1000 }
 
 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
 # ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick
diff --git a/tcl/target/omap5912.cfg b/tcl/target/omap5912.cfg
index c4ff40e..2f9338b 100644
--- a/tcl/target/omap5912.cfg
+++ b/tcl/target/omap5912.cfg
@@ -14,7 +14,7 @@ if { [info exists CPUTAPID] } {
    set _CPUTAPID 0x0692602f
 }
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 # NOTE: presumes irlen 38 is the C55x DSP, matching BSDL for
 # its standalone siblings (like TMS320VC5502) of the same era
diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg
index fd9ff4c..30cf23c 100644
--- a/tcl/target/omapl138.cfg
+++ b/tcl/target/omapl138.cfg
@@ -52,8 +52,8 @@ $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg
index d53b99a..51a6bbd 100644
--- a/tcl/target/pic32mx.cfg
+++ b/tcl/target/pic32mx.cfg
@@ -23,7 +23,7 @@ if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE 0x4000
 }
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 #jtag scan chain
diff --git a/tcl/target/psoc4.cfg b/tcl/target/psoc4.cfg
index 544e109..b568282 100644
--- a/tcl/target/psoc4.cfg
+++ b/tcl/target/psoc4.cfg
@@ -36,7 +36,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
 
-adapter_khz 1500
+adapter speed 1500
 
 # Reset, bloody PSoC 4 reset
 #
@@ -118,7 +118,7 @@ proc ocd_process_reset_inner { MODE } {
 	}
 
 	if { ! [info exists PSOC4_USE_ACQUIRE] } {
-		if { 0 == [string compare [adapter_name] kitprog ] } {
+		if { 0 == [string compare [adapter name] kitprog ] } {
 			set PSOC4_USE_ACQUIRE 1
 		} else {
 			set PSOC4_USE_ACQUIRE 0
@@ -138,7 +138,7 @@ proc ocd_process_reset_inner { MODE } {
 	$t invoke-event reset-assert-pre
 
 	if { $halt && $PSOC4_USE_ACQUIRE } {
-		catch { [adapter_name] acquire_psoc }
+		catch { [adapter name] acquire_psoc }
 		$t arp_examine
 	} else {
 		if { $PSOC4_TEST_MODE_WORKAROUND } {
diff --git a/tcl/target/psoc6.cfg b/tcl/target/psoc6.cfg
index fc0c711..51d032b 100644
--- a/tcl/target/psoc6.cfg
+++ b/tcl/target/psoc6.cfg
@@ -6,7 +6,7 @@
 
 source [find target/swj-dp.tcl]
 
-adapter_khz 1000
+adapter speed 1000
 
 global _CHIPNAME
 if { [info exists CHIPNAME] } {
diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 3862425..73518bf 100644
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -28,8 +28,8 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
 # PXA255 comes out of reset using 3.6864 MHz oscillator.
 # Until the PLL kicks in, keep the JTAG clock slow enough
 # that we get no errors.
-adapter_khz 300
-$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
+adapter speed 300
+$_TARGETNAME configure -event "reset-start" { adapter speed 300 }
 
 # both TRST and SRST are *required* for debug
 # DCSR is often accessed with SRST active
@@ -38,11 +38,11 @@ reset_config trst_and_srst separate srst_nogate
 # reset processing that works with PXA
 proc init_reset {mode} {
 	# assert both resets; equivalent to power-on reset
-	jtag_reset 1 1
+	adapter assert trst assert srst
 
 	# drop TRST after at least 32 cycles
 	sleep 1
-	jtag_reset 0 1
+	adapter deassert trst assert srst
 
 	# minimum 32 TCK cycles to wake up the controller
 	runtest 50
@@ -51,7 +51,7 @@ proc init_reset {mode} {
 	jtag arp_init
 
 	# ... and take it out of reset
-	jtag_reset 0 0
+	adapter deassert trst deassert srst
 }
 
 proc jtag_init {} {
diff --git a/tcl/target/pxa270.cfg b/tcl/target/pxa270.cfg
index 95f7f16..bd904b5 100644
--- a/tcl/target/pxa270.cfg
+++ b/tcl/target/pxa270.cfg
@@ -34,9 +34,9 @@ if { [info exists CPUTAPID3] } {
    set _CPUTAPID3 0x89265013
 }
 
-# set adapter_nsrst_delay to the delay introduced by your reset circuit
+# set adapter srst delay to the delay introduced by your reset circuit
 # the rest of the needed delays are built into the openocd program
-adapter_nsrst_delay 260
+adapter srst delay 260
 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
 # the rest of the needed delays are built into the openocd program
 jtag_ntrst_delay 250
diff --git a/tcl/target/pxa3xx.cfg b/tcl/target/pxa3xx.cfg
index c459f6e..1a4539c 100644
--- a/tcl/target/pxa3xx.cfg
+++ b/tcl/target/pxa3xx.cfg
@@ -59,9 +59,9 @@ if { [info exists CPUTAPID_PXA32X_C0] } {
    set _CPUTAPID_PXA32X_C0 0x7E642013
 }
 
-# set adapter_nsrst_delay to the delay introduced by your reset circuit
+# set adapter srst delay to the delay introduced by your reset circuit
 # the rest of the needed delays are built into the openocd program
-adapter_nsrst_delay 260
+adapter srst delay 260
 
 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
 # the rest of the needed delays are built into the openocd program
diff --git a/tcl/target/qualcomm_qca4531.cfg b/tcl/target/qualcomm_qca4531.cfg
index 3d21578..0b046b8 100644
--- a/tcl/target/qualcomm_qca4531.cfg
+++ b/tcl/target/qualcomm_qca4531.cfg
@@ -38,12 +38,12 @@ reset_config none srst_pulls_trst
 # For SRST based variant we still need proper timings.
 # For ETH part the reset should be asserted at least for 10ms
 # Since there is no other information let's take 100ms to be sure.
-adapter_nsrst_assert_width 100
+adapter srst pulse_width 100
 
 # according to the SoC documentation it should take at least 5ms from
 # reset end till bootstrap end. In the practice we need 8ms to get JTAG back
 # to live.
-adapter_nsrst_delay 8
+adapter srst delay 8
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $_CHIPNAME
diff --git a/tcl/target/readme.txt b/tcl/target/readme.txt
index f028b11..91bb2d5 100644
--- a/tcl/target/readme.txt
+++ b/tcl/target/readme.txt
@@ -26,16 +26,15 @@ assumed that all write-protect mechanisms should be disabled.
 flash write_image [file] <parameters>
 verify_image [file] <parameters>
 
-4. adapter_khz sets the maximum speed (or alternatively RCLK). If invoked
+4. adapter speed sets the maximum speed (or alternatively RCLK). If invoked
 multiple times only the last setting is used.
 
 interface/xxx.cfg files are always executed *before* target/xxx.cfg
-files, so any adapter_khz in interface/xxx.cfg will be overridden by
-target/xxx.cfg. adapter_khz in interface/xxx.cfg would then, effectively,
+files, so any adapter speed in interface/xxx.cfg will be overridden by
+target/xxx.cfg. adapter speed in interface/xxx.cfg would then, effectively,
 set the default JTAG speed.
 
 Note that a target/xxx.cfg file can invoke another target/yyy.cfg file,
 so one can create target subtype configurations where e.g. only
 amount of DRAM, oscillator speeds differ and having a single
 config file for the default/common settings.
-
diff --git a/tcl/target/renesas_r7s72100.cfg b/tcl/target/renesas_r7s72100.cfg
index f9466fc..5220b3c 100644
--- a/tcl/target/renesas_r7s72100.cfg
+++ b/tcl/target/renesas_r7s72100.cfg
@@ -1,4 +1,4 @@
-# Renesas R-Car RZ/A1H
+# Renesas RZ/A1H
 # https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza1h.html
 
 if { [info exists DAP_TAPID] } {
diff --git a/tcl/target/renesas_r8a7790.cfg b/tcl/target/renesas_r8a7790.cfg
deleted file mode 100644
index a662b6b..0000000
--- a/tcl/target/renesas_r8a7790.cfg
+++ /dev/null
@@ -1,36 +0,0 @@
-# Renesas R-Car H2
-# https://www.renesas.com/en-us/solutions/automotive/products/rcar-h2.html
-
-if { [info exists DAP_TAPID] } {
-	set _DAP_TAPID $DAP_TAPID
-} else {
-	set _DAP_TAPID 0x4ba00477
-}
-
-if { [info exists CHIPNAME] } {
-	set _CHIPNAME $CHIPNAME
-} else {
-	set _CHIPNAME r8a7790
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
-
-# Configuring only one core using DAP.
-# Base addresses of Cortex A15 cores:
-#  core 0  -  0x800B0000
-#  core 1  -  0x800B2000
-#  core 2  -  0x800B4000
-#  core 3  -  0x800B6000
-# Base addresses of Cortex A7 cores (not supported yet):
-#  core 0  -  0x800F0000
-#  core 1  -  0x800F2000
-#  core 2  -  0x800F4000
-#  core 3  -  0x800F6000
-set _TARGETNAME $_CHIPNAME.ca15.
-dap create ${_CHIPNAME}.dap -chain-position $_CHIPNAME.cpu
-target create ${_TARGETNAME}0 cortex_a -dap ${_CHIPNAME}.dap -coreid 0 -dbgbase 0x800B0000
-target create ${_TARGETNAME}1 cortex_a -dap ${_CHIPNAME}.dap -coreid 1 -dbgbase 0x800B2000 -defer-examine
-target create ${_TARGETNAME}2 cortex_a -dap ${_CHIPNAME}.dap -coreid 2 -dbgbase 0x800B4000 -defer-examine
-target create ${_TARGETNAME}3 cortex_a -dap ${_CHIPNAME}.dap -coreid 3 -dbgbase 0x800B6000 -defer-examine
-
-targets ${_TARGETNAME}0
diff --git a/tcl/target/renesas_r8a7791.cfg b/tcl/target/renesas_r8a7791.cfg
deleted file mode 100644
index f93cbb8..0000000
--- a/tcl/target/renesas_r8a7791.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-# Renesas R-Car M2
-# https://www.renesas.com/en-us/solutions/automotive/products/rcar-m2.html
-
-if { [info exists DAP_TAPID] } {
-	set _DAP_TAPID $DAP_TAPID
-} else {
-	set _DAP_TAPID 0x4ba00477
-}
-
-if { [info exists CHIPNAME] } {
-	set _CHIPNAME $CHIPNAME
-} else {
-	set _CHIPNAME r8a7791
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
-
-# Configuring only one core using DAP.
-# Base addresses of cores:
-#  core 0  -  0x800B0000
-#  core 1  -  0x800B2000
-set _TARGETNAME $_CHIPNAME.ca15.
-dap create ${_CHIPNAME}.dap -chain-position $_CHIPNAME.cpu
-target create ${_TARGETNAME}0 cortex_a -dap ${_CHIPNAME}.dap -coreid 0 -dbgbase 0x800B0000
-target create ${_TARGETNAME}1 cortex_a -dap ${_CHIPNAME}.dap -coreid 1 -dbgbase 0x800B2000 -defer-examine
-
-targets ${_TARGETNAME}0
diff --git a/tcl/target/renesas_r8a7794.cfg b/tcl/target/renesas_r8a7794.cfg
deleted file mode 100644
index e3e2724..0000000
--- a/tcl/target/renesas_r8a7794.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-# Renesas R-Car E2
-# https://www.renesas.com/en-us/solutions/automotive/products/rcar-e2.html
-
-if { [info exists DAP_TAPID] } {
-	set _DAP_TAPID $DAP_TAPID
-} else {
-	set _DAP_TAPID 0x4ba00477
-}
-
-if { [info exists CHIPNAME] } {
-	set _CHIPNAME $CHIPNAME
-} else {
-	set _CHIPNAME r8a7794
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
-
-# Configuring only one core using DAP.
-# Base addresses of cores:
-#  core 0  -  0x800F0000
-#  core 1  -  0x800F2000
-set _TARGETNAME $_CHIPNAME.ca7.
-dap create ${_CHIPNAME}.dap -chain-position $_CHIPNAME.cpu
-target create ${_TARGETNAME}0 cortex_a -dap ${_CHIPNAME}.dap -coreid 0 -dbgbase 0x800F0000
-target create ${_TARGETNAME}1 cortex_a -dap ${_CHIPNAME}.dap -coreid 1 -dbgbase 0x800F2000 -defer-examine
-
-targets ${_TARGETNAME}0
diff --git a/tcl/target/renesas_rcar_gen2.cfg b/tcl/target/renesas_rcar_gen2.cfg
new file mode 100644
index 0000000..91baa6c
--- /dev/null
+++ b/tcl/target/renesas_rcar_gen2.cfg
@@ -0,0 +1,125 @@
+# Renesas R-Car Generation 2 SOCs
+# - There are a combination of Cortex-A15s and Cortex-A7s for each Gen2 SOC
+# - Each SOC can boot through any of the, up to 2, core types that it has
+#   e.g. H2 can boot through Cortex-A15 or Cortex-A7
+
+# Supported Gen2 SOCs and their cores:
+# H2:  Cortex-A15 x 4, Cortex-A7 x 4
+# M2:  Cortex-A15 x 2
+# V2H: Cortex-A15 x 2
+# M2N: Cortex-A15 x 2
+# E2:                  Cortex-A7 x 2
+
+# Usage:
+# There are 2 configuration options:
+# SOC:       Selects the supported SOC. (Default 'H2')
+# BOOT_CORE: Selects the booting core. 'CA15', or 'CA7'
+#            Defaults to 'CA15' if the SOC has one, else defaults to 'CA7'
+
+if { [info exists SOC] } {
+	set _soc $SOC
+} else {
+	set _soc H2
+}
+
+# Set configuration for each SOC and the default 'BOOT_CORE'
+switch $_soc {
+	H2 {
+		set _CHIPNAME r8a7790
+		set _num_ca15 4
+		set _num_ca7 4
+		set _boot_core CA15
+	}
+	M2 {
+		set _CHIPNAME r8a7791
+		set _num_ca15 2
+		set _num_ca7 0
+		set _boot_core CA15
+	}
+	V2H {
+		set _CHIPNAME r8a7792
+		set _num_ca15 2
+		set _num_ca7 0
+		set _boot_core CA15
+	}
+	M2N {
+		set _CHIPNAME r8a7793
+		set _num_ca15 2
+		set _num_ca7 0
+		set _boot_core CA15
+	}
+	E2 {
+		set _CHIPNAME r8a7794
+		set _num_ca15 0
+		set _num_ca7 2
+		set _boot_core CA7
+	}
+	default {
+		error "'$_soc' is invalid!"
+	}
+}
+
+# If configured, override the default 'CHIPNAME'
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+}
+
+# If configured, override the default 'BOOT_CORE'
+if { [info exists BOOT_CORE] } {
+	set _boot_core $BOOT_CORE
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+
+echo "\t$_soc - $_num_ca15 CA15(s), $_num_ca7 CA7(s)"
+echo "\tBoot Core - $_boot_core\n"
+
+set _DAPNAME $_CHIPNAME.dap
+
+# TAP and DAP
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
+dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
+
+set CA15_DBGBASE {0x800B0000 0x800B2000 0x800B4000 0x800B6000}
+set CA7_DBGBASE  {0x800F0000 0x800F2000 0x800F4000 0x800F6000}
+
+set smp_targets ""
+
+proc setup_ca {core_name dbgbase num boot} {
+	global _CHIPNAME
+	global _DAPNAME
+	global smp_targets
+	for { set _core 0 } { $_core < $num } { incr _core } {
+		set _TARGETNAME $_CHIPNAME.$core_name.$_core
+		set _CTINAME $_TARGETNAME.cti
+		set _command "target create $_TARGETNAME cortex_a -dap $_DAPNAME \
+			-coreid $_core -dbgbase [lindex $dbgbase $_core]"
+		if { $_core == 0  && $boot == 1 } {
+			set _targets "$_TARGETNAME"
+		} else {
+			set _command "$_command -defer-examine"
+		}
+		set smp_targets "$smp_targets $_TARGETNAME"
+		eval $_command
+	}
+}
+
+# Organize target list based on the boot core
+if { [string equal $_boot_core CA15] } {
+	setup_ca a15 $CA15_DBGBASE $_num_ca15 1
+	setup_ca a7  $CA7_DBGBASE  $_num_ca7 0
+} elseif { [string equal $_boot_core CA7] } {
+	setup_ca a7  $CA7_DBGBASE  $_num_ca7 1
+	setup_ca a15 $CA15_DBGBASE $_num_ca15 0
+} else {
+	setup_ca a15 $CA15_DBGBASE $_num_ca15 0
+	setup_ca a7  $CA7_DBGBASE  $_num_ca7 0
+}
+
+source [find target/renesas_rcar_reset_common.cfg]
+
+eval "target smp $smp_targets"
diff --git a/tcl/target/renesas_rcar_gen3.cfg b/tcl/target/renesas_rcar_gen3.cfg
index 2c478b2..72f185d 100644
--- a/tcl/target/renesas_rcar_gen3.cfg
+++ b/tcl/target/renesas_rcar_gen3.cfg
@@ -76,7 +76,7 @@ switch $_soc {
 		set _boot_core CA53
 	}
 	default {
-		echo "'$_soc' is invalid!"
+		error "'$_soc' is invalid!"
 	}
 }
 
@@ -166,4 +166,6 @@ if { [string equal $_boot_core CA57] } {
 	setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
 }
 
+source [find target/renesas_rcar_reset_common.cfg]
+
 eval "target smp $smp_targets"
diff --git a/tcl/target/renesas_rcar_reset_common.cfg b/tcl/target/renesas_rcar_reset_common.cfg
new file mode 100644
index 0000000..3e4579b
--- /dev/null
+++ b/tcl/target/renesas_rcar_reset_common.cfg
@@ -0,0 +1,14 @@
+# Renesas R-Car Gen2 Evaluation Board common settings
+
+reset_config trst_and_srst srst_nogate
+
+proc init_reset {mode} {
+    # Assert both resets: equivalent to a power-on reset
+    adapter assert trst assert srst
+
+    # Deassert TRST to begin TAP communication
+    adapter deassert trst assert srst
+
+    # TAP should now be responsive, validate the scan-chain
+    jtag arp_init
+}
diff --git a/tcl/target/renesas_s7g2.cfg b/tcl/target/renesas_s7g2.cfg
index 78fb3e8..b4be88f 100644
--- a/tcl/target/renesas_s7g2.cfg
+++ b/tcl/target/renesas_s7g2.cfg
@@ -48,4 +48,4 @@ if { ![using_hla] } {
 	cortex_m reset_config sysresetreq
 }
 
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/target/samsung_s3c2440.cfg b/tcl/target/samsung_s3c2440.cfg
index 2a0a915..a97659b 100644
--- a/tcl/target/samsung_s3c2440.cfg
+++ b/tcl/target/samsung_s3c2440.cfg
@@ -32,4 +32,3 @@ $_TARGETNAME configure -work-area-phys 0x200000 -work-area-size 0x4000 -work-are
 
 #reset configuration
 reset_config trst_and_srst
-
diff --git a/tcl/target/samsung_s3c2450.cfg b/tcl/target/samsung_s3c2450.cfg
index 1bc4f2d..2482557 100644
--- a/tcl/target/samsung_s3c2450.cfg
+++ b/tcl/target/samsung_s3c2450.cfg
@@ -7,11 +7,11 @@
 #
 # RCLK?
 #
-# adapter_khz 0
+# adapter speed 0
 #
 # Really low clock during reset?
 #
-# adapter_khz 1
+# adapter speed 1
 
 if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/samsung_s3c4510.cfg b/tcl/target/samsung_s3c4510.cfg
index 461d047..8bc5da5 100644
--- a/tcl/target/samsung_s3c4510.cfg
+++ b/tcl/target/samsung_s3c4510.cfg
@@ -21,4 +21,3 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
diff --git a/tcl/target/samsung_s3c6410.cfg b/tcl/target/samsung_s3c6410.cfg
index 88fe966..9f7c2cd 100644
--- a/tcl/target/samsung_s3c6410.cfg
+++ b/tcl/target/samsung_s3c6410.cfg
@@ -40,7 +40,7 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_C
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
 
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 #reset configuration
diff --git a/tcl/target/sharp_lh79532.cfg b/tcl/target/sharp_lh79532.cfg
index 6f2cf22..a464839 100644
--- a/tcl/target/sharp_lh79532.cfg
+++ b/tcl/target/sharp_lh79532.cfg
@@ -22,5 +22,3 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
-
diff --git a/tcl/target/sim3x.cfg b/tcl/target/sim3x.cfg
index ed46a3b..3d3fc5c 100755..100644
--- a/tcl/target/sim3x.cfg
+++ b/tcl/target/sim3x.cfg
@@ -48,9 +48,9 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
 
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
diff --git a/tcl/target/smp8634.cfg b/tcl/target/smp8634.cfg
index c13414c..e95f633 100644
--- a/tcl/target/smp8634.cfg
+++ b/tcl/target/smp8634.cfg
@@ -18,7 +18,7 @@ if { [info exists CPUTAPID] } {
    set _CPUTAPID 0x08630001
 }
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 reset_config trst_and_srst separate
diff --git a/tcl/target/snps_em_sk_fpga.cfg b/tcl/target/snps_em_sk_fpga.cfg
new file mode 100644
index 0000000..2f7fecb
--- /dev/null
+++ b/tcl/target/snps_em_sk_fpga.cfg
@@ -0,0 +1,33 @@
+#  Copyright (C) 2014-2015,2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+#  SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Xilinx Spartan-6 XC6SLX45  FPGA on EM Starter Kit v1.
+# Xilinx Spartan-6 XC6SLX150 FPGA on EM Starter Kit v2.
+#
+
+source [find cpu/arc/em.tcl]
+
+set _CHIPNAME arc-em
+set _TARGETNAME $_CHIPNAME.cpu
+
+# EM SK IDENTITY is 0x200444b1
+# EM SK v2 IDENTITY is 0x200044b1
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -expected-id 0x200444b1 \
+  -expected-id 0x200044b1
+
+set _coreid 0
+set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME \
+  -coreid 0 -dbgbase $_dbgbase -endian little
+
+# There is no SRST, so do a software reset
+$_TARGETNAME configure -event reset-assert "arc_em_reset $_TARGETNAME"
+
+arc_em_init_regs
+
+# vim:ft=tcl
diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg
index 7fffd2a..3cab4d1 100644
--- a/tcl/target/stellaris.cfg
+++ b/tcl/target/stellaris.cfg
@@ -68,7 +68,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 # NOTE: this may be increased by a reset-init handler, after it
 # configures and enables the PLL.  Or you might need to decrease
 # this, if you're using a slower clock.
-adapter_khz 500
+adapter speed 500
 
 source [find mem_helper.tcl]
 
@@ -132,7 +132,7 @@ proc reset_peripherals {family} {
 }
 
 $_TARGETNAME configure -event reset-start {
-	adapter_khz 500
+	adapter speed 500
 
 	#
 	# When nRST is asserted on most Stellaris devices, it clears some of
@@ -164,7 +164,7 @@ $_TARGETNAME configure -event reset-start {
 	} else {
 		if {![using_hla]} {
 		   # Tempest and Firestorm default to using NVIC VECTRESET
-		   # peripherals will need reseting manually, see proc reset_peripherals
+		   # peripherals will need resetting manually, see proc reset_peripherals
 		   cortex_m reset_config vectreset
 		}
 		# reset peripherals, based on code in
diff --git a/tcl/target/stm32f0x.cfg b/tcl/target/stm32f0x.cfg
index baac9b6..b20d036 100644
--- a/tcl/target/stm32f0x.cfg
+++ b/tcl/target/stm32f0x.cfg
@@ -52,9 +52,9 @@ set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
 
 # adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 reset_config srst_nogate
 
@@ -66,7 +66,7 @@ if {![using_hla]} {
 
 proc stm32f0x_default_reset_start {} {
 	# Reset clock is HSI (8 MHz)
-	adapter_khz 1000
+	adapter speed 1000
 }
 
 proc stm32f0x_default_examine_end {} {
@@ -86,7 +86,7 @@ proc stm32f0x_default_reset_init {} {
 	mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
 
 	# Boost JTAG frequency
-	adapter_khz 8000
+	adapter speed 8000
 }
 
 # Default hooks
diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg
index 471878d..3e85fb2 100644
--- a/tcl/target/stm32f1x.cfg
+++ b/tcl/target/stm32f1x.cfg
@@ -60,9 +60,9 @@ set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
 
 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg
index 1e8b94a..d790feb 100644
--- a/tcl/target/stm32f2x.cfg
+++ b/tcl/target/stm32f2x.cfg
@@ -28,9 +28,9 @@ if { [info exists WORKAREASIZE] } {
 # bit more to be on the safe side. Perhaps superstition, but if are
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index 86e9f59..e3f1a34 100644
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -28,9 +28,9 @@ if { [info exists WORKAREASIZE] } {
 # bit more to be on the safe side. Perhaps superstition, but if are
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -73,7 +73,7 @@ if {![using_hla]} {
 
 proc stm32f3x_default_reset_start {} {
 	# Reset clock is HSI (8 MHz)
-	adapter_khz 1000
+	adapter speed 1000
 }
 
 proc stm32f3x_default_examine_end {} {
@@ -93,7 +93,7 @@ proc stm32f3x_default_reset_init {} {
 	mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
 
 	# Boost JTAG frequency
-	adapter_khz 8000
+	adapter speed 8000
 }
 
 # Default hooks
diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index 09ce14a..b95e783 100644
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -58,9 +58,9 @@ flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
 # bit more to be on the safe side. Perhaps superstition, but if are
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
-adapter_khz 2000
+adapter speed 2000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -100,10 +100,10 @@ $_TARGETNAME configure -event reset-init {
 	mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
 
 	# Boost JTAG frequency
-	adapter_khz 8000
+	adapter speed 8000
 }
 
 $_TARGETNAME configure -event reset-start {
 	# Reduce speed since CPU speed will slow down to 16MHz with the reset
-	adapter_khz 2000
+	adapter speed 2000
 }
diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg
index ba1d12f..6ad4b65 100755..100644
--- a/tcl/target/stm32f7x.cfg
+++ b/tcl/target/stm32f7x.cfg
@@ -65,9 +65,9 @@ flash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME
 flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME
 
 # adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
-adapter_khz 2000
+adapter speed 2000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -162,12 +162,11 @@ $_TARGETNAME configure -event reset-init {
 	if {[using_jtag]} {
 		[[target current] cget -dap] memaccess 16
 	} {
-		adapter_khz 8000
+		adapter speed 8000
 	}
 }
 
 $_TARGETNAME configure -event reset-start {
 	# Reduce speed since CPU speed will slow down to 16MHz with the reset
-	adapter_khz 2000
+	adapter speed 2000
 }
-
diff --git a/tcl/target/stm32g0x.cfg b/tcl/target/stm32g0x.cfg
new file mode 100644
index 0000000..50836ea
--- /dev/null
+++ b/tcl/target/stm32g0x.cfg
@@ -0,0 +1,88 @@
+# script for stm32g0x family
+
+#
+# stm32g0 devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32g0x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# Smallest proposed target has 8kB ram, use 4kB by default to avoid surprises
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x1000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	# Section 37.5.5 - corresponds to Cortex-M0+
+	set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+# reasonable default
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+proc stm32g0x_default_reset_start {} {
+	# Reset clock is HSI16 (16 MHz)
+	adapter speed 2000
+}
+
+proc stm32g0x_default_examine_end {} {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+	mmw 0x40015804 0x00000006 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0x40015808 0x00001800 0
+}
+
+proc stm32g0x_default_reset_init {} {
+	# Increase clock to 64 Mhz
+	mmw 0x40022000 0x00000002 0x00000005	;# FLASH_ACR: Latency = 2
+	mww 0x4002100C 0x30000802				;# RCC_PLLCFGR = PLLR=/2, PLLN=8, PLLM=/1, PLLSRC=0x2
+	mmw 0x40021000 0x01000000 0x00000000	;# RCC_CR |= PLLON
+	mmw 0x40021008 0x00000002 0x00000005	;# RCC_CFGR: SW=PLLRCLK
+
+	# Boost JTAG frequency
+	adapter speed 4000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32g0x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32g0x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32g0x_default_reset_init }
diff --git a/tcl/target/stm32g4x.cfg b/tcl/target/stm32g4x.cfg
new file mode 100644
index 0000000..9f144a0
--- /dev/null
+++ b/tcl/target/stm32g4x.cfg
@@ -0,0 +1,103 @@
+# script for stm32g4x family
+
+#
+# stm32g4 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32g4x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# Smallest current target has 32kB ram, use 16kB by default to avoid surprises
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x4000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		# See STM Document RM0440
+		# Section 46.6.3 - corresponds to Cortex-M4 r0p1
+		set _CPUTAPID 0x4ba00477
+	} {
+		set _CPUTAPID 0x2ba01477
+	}
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+if { [info exists QUADSPI] && $QUADSPI } {
+	set a [llength [flash list]]
+	set _QSPINAME $_CHIPNAME.qspi
+	flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+}
+
+# reasonable default
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+	# CPU comes out of reset with HSION | HSIRDY.
+	# Use HSI 16 MHz clock, compliant even with VOS == 2.
+	# 1 WS compliant with VOS == 2 and 16 MHz.
+	mmw 0x40022000 0x00000001 0x0000000E	;# FLASH_ACR: Latency = 1
+	mmw 0x40021000 0x00000100 0x00000000	;# RCC_CR |= HSION
+	mmw 0x40021008 0x00000001 0x00000002	;# RCC_CFGR: SW=HSI16
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reset clock is HSI (16 MHz)
+	adapter speed 2000
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0042008 0x00001800 0
+}
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg
index 0bfc43d..2d92eca 100644
--- a/tcl/target/stm32h7x.cfg
+++ b/tcl/target/stm32h7x.cfg
@@ -12,6 +12,39 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME stm32h7x
 }
 
+if { [info exists DUAL_BANK] } {
+	set $_CHIPNAME.DUAL_BANK $DUAL_BANK
+	unset DUAL_BANK
+} else {
+	set $_CHIPNAME.DUAL_BANK 0
+}
+
+if { [info exists DUAL_CORE] } {
+	set $_CHIPNAME.DUAL_CORE $DUAL_CORE
+	unset DUAL_CORE
+} else {
+	set $_CHIPNAME.DUAL_CORE 0
+}
+
+# Issue a warning when hla is used, and fallback to single core configuration
+if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
+	echo "Warning : hla does not support multicore debugging"
+	set $_CHIPNAME.DUAL_CORE 0
+}
+
+if { [info exists USE_CTI] } {
+	set $_CHIPNAME.USE_CTI $USE_CTI
+	unset USE_CTI
+} else {
+	set $_CHIPNAME.USE_CTI 0
+}
+
+# Issue a warning when DUAL_CORE=0 and USE_CTI=1, and fallback to USE_CTI=0
+if { ![set $_CHIPNAME.DUAL_CORE] && [set $_CHIPNAME.USE_CTI] } {
+	echo "Warning : could not use CTI with a single core device, CTI is disabled"
+	set $_CHIPNAME.USE_CTI 0
+}
+
 set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
@@ -40,18 +73,41 @@ if {[using_jtag]} {
  swj_newdap $_CHIPNAME bs -irlen 5
 }
 
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+if {![using_hla]} {
+	# STM32H7 provides an APB-AP at access port 2, which allows the access to
+	# the debug and trace features on the system APB System Debug Bus (APB-D).
+	target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
+}
+
+target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
+
+$_CHIPNAME.cpu0 configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.bank1.cpu0 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0
+
+if {[set $_CHIPNAME.DUAL_BANK]} {
+	flash bank $_CHIPNAME.bank2.cpu0 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu0
+}
+
+if {[set $_CHIPNAME.DUAL_CORE]} {
+	target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3
 
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+	$_CHIPNAME.cpu1 configure -work-area-phys 0x38000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+	flash bank $_CHIPNAME.bank1.cpu1 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu1
+
+	if {[set $_CHIPNAME.DUAL_BANK]} {
+		flash bank $_CHIPNAME.bank2.cpu1 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu1
+	}
+}
 
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME
+# Make sure that cpu0 is selected
+targets $_CHIPNAME.cpu0
 
 # Clock after reset is HSI at 64 MHz, no need of PLL
-adapter_khz 1800
+adapter speed 1800
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -72,7 +128,11 @@ reset_config srst_only srst_nogate
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
-   cortex_m reset_config sysresetreq
+	$_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
+
+	if {[set $_CHIPNAME.DUAL_CORE]} {
+		$_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
+	}
 
    # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
    # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
@@ -83,31 +143,133 @@ if {![using_hla]} {
    $_CHIPNAME.dap apcsw 0x08000000 0x08000000
 }
 
-$_TARGETNAME configure -event examine-end {
+$_CHIPNAME.cpu0 configure -event examine-end {
 	# Enable D3 and D1 DBG clocks
 	# DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
-	mmw 0x5C001004 0x00600000 0
+	stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
 
 	# Enable debug during low power modes (uses more power)
-	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3 & D1 Domains
-	mmw 0x5C001004 0x00000187 0
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3, D2 & D1 Domains
+	stm32h7x_dbgmcu_mmw 0x004 0x000001BF 0
 
 	# Stop watchdog counters during halt
 	# DBGMCU_APB3FZ1 |= WWDG1
-	mmw 0x5C001034 0x00000040 0
-	# DBGMCU_APB4FZ1 |= WDGLSD1
-	mmw 0x5C001054 0x00040000 0
+	stm32h7x_dbgmcu_mmw 0x034 0x00000040 0
+	# DBGMCU_APB1LFZ1 |= WWDG2
+	stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
+	# DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
+	stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
 }
 
-$_TARGETNAME configure -event trace-config {
+$_CHIPNAME.cpu0 configure -event trace-config {
 	# Set TRACECLKEN; TRACE_MODE is set to async; when using sync
 	# change this value accordingly to configure trace pins
 	# assignment
-	mmw 0x5C001004 0x00100000 0
+	stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
 }
 
-$_TARGETNAME configure -event reset-init {
+$_CHIPNAME.cpu0 configure -event reset-init {
 	# Clock after reset is HSI at 64 MHz, no need of PLL
-	adapter_khz 4000
+	adapter speed 4000
+}
+
+if {[set $_CHIPNAME.DUAL_CORE]} {
+	$_CHIPNAME.cpu1 configure -event examine-end {
+		# get _CHIPNAME from the current target
+		set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+		global $_CHIPNAME.USE_CTI
+
+		# Stop watchdog counters during halt
+		# DBGMCU_APB3FZ2 |= WWDG1
+		stm32h7x_dbgmcu_mmw 0x038 0x00000040 0
+		# DBGMCU_APB1LFZ2 |= WWDG2
+		stm32h7x_dbgmcu_mmw 0x040 0x00000800 0
+		# DBGMCU_APB4FZ2 |= WDGLSD1 | WDGLSD2
+		stm32h7x_dbgmcu_mmw 0x058 0x000C0000 0
+
+		if {[set $_CHIPNAME.USE_CTI]} {
+			stm32h7x_cti_start
+		}
+	}
+}
+
+# like mrw, but with target selection
+proc stm32h7x_mrw {used_target reg} {
+	set value ""
+	$used_target mem2array value 32 $reg 1
+	return $value(0)
+}
+
+# like mmw, but with target selection
+proc stm32h7x_mmw {used_target reg setbits clearbits} {
+	set old [stm32h7x_mrw $used_target $reg]
+	set new [expr ($old & ~$clearbits) | $setbits]
+	$used_target mww $reg $new
+}
+
+# mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base
+# this procedure will use the mem_ap on AP2 whenever possible
+proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
+	# use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address
+	if {![using_hla]} {
+		# get _CHIPNAME from the current target
+		set _CHIPNAME [regsub ".(cpu|ap)\\d*$" [target current] ""]
+		set used_target $_CHIPNAME.ap2
+		set reg_addr [expr 0xE00E1000 + $reg_offset]
+	} {
+		set used_target [target current]
+		set reg_addr [expr 0x5C001000 + $reg_offset]
+	}
+
+	stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
 }
 
+if {[set $_CHIPNAME.USE_CTI]} {
+	# create CTI instances for both cores
+	cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -ctibase 0xE0043000
+	cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -ctibase 0xE0043000
+
+	$_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }
+	$_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }
+
+	$_CHIPNAME.cpu0 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
+	$_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
+
+	proc stm32h7x_cti_start {} {
+		# get _CHIPNAME from the current target
+		set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+
+		# Configure Cores' CTIs to halt each other
+		# TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
+		$_CHIPNAME.cti0 write INEN0 0x1
+		$_CHIPNAME.cti0 write OUTEN0 0x1
+		$_CHIPNAME.cti1 write INEN0 0x1
+		$_CHIPNAME.cti1 write OUTEN0 0x1
+
+		# enable CTIs
+		$_CHIPNAME.cti0 enable on
+		$_CHIPNAME.cti1 enable on
+	}
+
+	proc stm32h7x_cti_stop {} {
+		# get _CHIPNAME from the current target
+		set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+
+		$_CHIPNAME.cti0 enable off
+		$_CHIPNAME.cti1 enable off
+	}
+
+	proc stm32h7x_cti_prepare_restart_all {} {
+		stm32h7x_cti_prepare_restart cti0
+		stm32h7x_cti_prepare_restart cti1
+	}
+
+	proc stm32h7x_cti_prepare_restart {cti} {
+		# get _CHIPNAME from the current target
+		set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+
+		# Acknowlodge EDBGRQ at TRIGOUT0
+		$_CHIPNAME.$cti write INACK 0x01
+		$_CHIPNAME.$cti write INACK 0x00
+	}
+}
diff --git a/tcl/target/stm32h7x_dual_bank.cfg b/tcl/target/stm32h7x_dual_bank.cfg
index 7e342f9..a88d70d 100644
--- a/tcl/target/stm32h7x_dual_bank.cfg
+++ b/tcl/target/stm32h7x_dual_bank.cfg
@@ -1,7 +1,6 @@
 # script for stm32h7x family (dual flash bank)
-source [find target/stm32h7x.cfg]
 
 # STM32H7xxxI 2Mo have a dual bank flash.
-# Add the second flash bank.
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME stm32h7x 0x08100000 0 0 0 $_TARGETNAME
+set DUAL_BANK 1
+
+source [find target/stm32h7x.cfg]
diff --git a/tcl/target/stm32l0.cfg b/tcl/target/stm32l0.cfg
index ec5d546..7653d13 100644
--- a/tcl/target/stm32l0.cfg
+++ b/tcl/target/stm32l0.cfg
@@ -24,9 +24,9 @@ if { [info exists WORKAREASIZE] } {
 
 # JTAG speed should be <= F_CPU/6.
 # F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
-adapter_khz 300
+adapter speed 300
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 if { [info exists CPUTAPID] } {
     set _CPUTAPID $CPUTAPID
@@ -61,13 +61,16 @@ proc stm32l0_enable_HSI16 {} {
 	echo "STM32L0: Enabling HSI16"
 
 	# Set HSI16ON in RCC_CR (leave MSI enabled)
-	mww 0x40021000 0x00000101
+    mmw 0x40021000 0x00000101 0
 
 	# Set HSI16 as SYSCLK (RCC_CFGR)
-	mww 0x4002100c 0x00000001
+	mmw 0x4002100c 0x00000001 0
+
+	# Wait until System clock switches to HSI16
+	while { ([ mrw 0x4002100c ] & 0x0c) != 0x04 } { }
 
 	# Increase speed
-	adapter_khz 2500
+	adapter speed 2500
 }
 
 $_TARGETNAME configure -event reset-init {
@@ -75,7 +78,7 @@ $_TARGETNAME configure -event reset-init {
 }
 
 $_TARGETNAME configure -event reset-start {
-	adapter_khz 300
+	adapter speed 300
 }
 
 $_TARGETNAME configure -event examine-end {
diff --git a/tcl/target/stm32l1.cfg b/tcl/target/stm32l1.cfg
index 054fa9b..a81d7c7 100644
--- a/tcl/target/stm32l1.cfg
+++ b/tcl/target/stm32l1.cfg
@@ -23,9 +23,9 @@ if { [info exists WORKAREASIZE] } {
 
 # JTAG speed should be <= F_CPU/6.
 # F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
-adapter_khz 300
+adapter speed 300
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -73,13 +73,13 @@ proc stm32l_enable_HSI {} {
 	echo "STM32L: Enabling HSI"
 
 	# Set HSION in RCC_CR
-	mww 0x40023800 0x00000101
+	mmw 0x40023800 0x00000101 0
 
 	# Set HSI as SYSCLK
-	mww 0x40023808 0x00000001
+	mmw 0x40023808 0x00000001 0
 
 	# Increase JTAG speed
-	adapter_khz 2000
+	adapter speed 2000
 }
 
 $_TARGETNAME configure -event reset-init {
@@ -87,7 +87,7 @@ $_TARGETNAME configure -event reset-init {
 }
 
 $_TARGETNAME configure -event reset-start {
-	adapter_khz 300
+	adapter speed 300
 }
 
 $_TARGETNAME configure -event examine-end {
diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg
index 496b47a..46e6f7e 100644
--- a/tcl/target/stm32l4x.cfg
+++ b/tcl/target/stm32l4x.cfg
@@ -56,9 +56,9 @@ flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
 #
 # Note that there is a pretty wide band where things are
 # more or less stable, see http://openocd.zylin.com/#/c/3366/
-adapter_khz 500
+adapter speed 500
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -78,12 +78,12 @@ $_TARGETNAME configure -event reset-init {
 	mww 0x40022000 0x00000103   ;# FLASH_ACR = PRFTBE | 3(Latency)
 	mww 0x40021000 0x00000099   ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
 	# Boost JTAG frequency
-	adapter_khz 4000
+	adapter speed 4000
 }
 
 $_TARGETNAME configure -event reset-start {
 	# Reset clock is MSI (4 MHz)
-	adapter_khz 500
+	adapter speed 500
 }
 
 $_TARGETNAME configure -event examine-end {
diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg
new file mode 100644
index 0000000..f2ba94e
--- /dev/null
+++ b/tcl/target/stm32mp15x.cfg
@@ -0,0 +1,121 @@
+# STMicroelectronics STM32MP15x (Single/Dual Cortex-A7 plus Cortex-M4)
+# http://www.st.com/stm32mp1
+
+# HLA does not support multi-cores nor custom CSW nor AP other than 0
+if { [using_hla] } {
+	echo "ERROR: HLA transport cannot work with this target."
+	echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp15x_dk2.cfg\"."
+	shutdown
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32mp15x
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} else {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Chip Level TAP Controller, only in jtag mode
+if { [info exists CLCTAPID] } {
+	set _CLCTAPID $CLCTAPID
+} else {
+	set _CLCTAPID 0x06500041
+}
+
+swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
+if { [using_jtag] } {
+	jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
+
+# FIXME: Cortex-M code requires target accessible during reset, but this is not possible in STM32MP1
+# so defer-examine it until the reset framework get merged
+# NOTE: keep ap-num and dbgbase to speed-up examine after reset
+# NOTE: do not change the order of target create
+target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
+target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
+target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000
+target create $_CHIPNAME.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
+
+targets $_CHIPNAME.cpu0
+
+target smp $_CHIPNAME.cpu0 $_CHIPNAME.cpu1
+$_CHIPNAME.cpu0 cortex_a maskisr on
+$_CHIPNAME.cpu1 cortex_a maskisr on
+$_CHIPNAME.cpu0 cortex_a dacrfixup on
+$_CHIPNAME.cpu1 cortex_a dacrfixup on
+
+cti create $_CHIPNAME.cti.sys  -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE0094000
+cti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE00D8000
+cti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE00D9000
+cti create $_CHIPNAME.cti.cm4  -dap $_CHIPNAME.dap -ap-num 2 -ctibase 0xE0043000
+
+# interface does not work while srst is asserted
+# this is target specific, valid for every board
+# Errata "2.3.5 Incorrect reset of glitch-free kernel clock switch" requires
+# srst to force VDDCORE power cycle or pull srst_core. Both cases reset the
+# debug unit, behavior equivalent to "srst_pulls_trst"
+reset_config srst_gates_jtag srst_pulls_trst
+
+adapter speed 5000
+adapter srst pulse_width 200
+# bootrom has an internal timeout of 1 second for detecting the boot flash.
+# wait at least 1 second to guarantee we are out of bootrom
+adapter srst delay 1100
+
+add_help_text axi_secure "Set secure mode for following AXI accesses"
+proc axi_secure {} {
+	$::_CHIPNAME.dap apsel 0
+	$::_CHIPNAME.dap apcsw 0x10006000
+}
+
+add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
+proc axi_nsecure {} {
+	$::_CHIPNAME.dap apsel 0
+	$::_CHIPNAME.dap apcsw 0x30006000
+}
+
+axi_secure
+
+proc dbgmcu_enable_debug {} {
+	# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
+	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
+}
+
+proc toggle_cpu0_dbg_claim0 {} {
+	# toggle CPU0 DBG_CLAIM[0]
+	$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
+	$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
+}
+
+proc detect_cpu1 {} {
+	$::_CHIPNAME.ap1 mem2array cpu1_prsr 32 0xE00D2314 1
+	set dual_core [expr $cpu1_prsr(0) & 1]
+	if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
+}
+
+# FIXME: most of handler below will be removed once reset framework get merged
+$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;dap init;catch {$::_CHIPNAME.dap apid 1}}
+$_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug}
+$_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
+$_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}
+$_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
+$_CHIPNAME.cm4  configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
+$_CHIPNAME.ap1  configure -event examine-start       {dap init}
+$_CHIPNAME.ap2  configure -event examine-start       {dbgmcu_enable_debug}
+$_CHIPNAME.cpu0 configure -event examine-end         {detect_cpu1}
+$_CHIPNAME.ap2  configure -event examine-end         {$::_CHIPNAME.cm4 arp_examine}
diff --git a/tcl/target/stm32wbx.cfg b/tcl/target/stm32wbx.cfg
new file mode 100644
index 0000000..90f53bb
--- /dev/null
+++ b/tcl/target/stm32wbx.cfg
@@ -0,0 +1,103 @@
+# script for stm32wbx family
+
+#
+# stm32wb devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32wbx
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x6ba00477
+   } else {
+      # SWD IDCODE (single drop, arm)
+      set _CPUTAPID 0x6ba02477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+    # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
+    # Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
+    # 2 WS compliant with VOS=Range1 and 24 MHz.
+    mmw 0x58004000 0x00000102 0  ;# FLASH_ACR |= PRFTBE | 2(Latency)
+    mmw 0x58000000 0x00000091 0  ;# RCC_CR = MSI_ON | MSI Range 24 MHz
+    # Boost JTAG frequency
+    adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+    # Reset clock is MSI (4 MHz)
+    adapter speed 500
+}
+
+$_TARGETNAME configure -event examine-end {
+    # Enable debug during low power modes (uses more power)
+    # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+    mmw 0xE0042004 0x00000007 0
+
+    # Stop watchdog counters during halt
+    # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
+    mmw 0xE004203C 0x00001800 0
+}
+
+$_TARGETNAME configure -event trace-config {
+    # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+    # change this value accordingly to configure trace pins
+    # assignment
+    mmw 0xE0042004 0x00000020 0
+}
diff --git a/tcl/target/stm32wlx.cfg b/tcl/target/stm32wlx.cfg
new file mode 100644
index 0000000..98c9a7e
--- /dev/null
+++ b/tcl/target/stm32wlx.cfg
@@ -0,0 +1,100 @@
+# script for stm32wlx family
+
+#
+# stm32wl devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32wlx
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 20kB
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x5000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} else {
+		# SWD IDCODE (single drop, arm)
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+	swj_newdap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+	# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
+	# Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
+	# 2 WS compliant with VOS=Range1 and 24 MHz.
+	mmw 0x58004000 0x00000102 0  ;# FLASH_ACR |= PRFTEN | 2(Latency)
+	mmw 0x58000000 0x00000091 0  ;# RCC_CR = MSI_ON | MSI Range 24 MHz
+	# Boost JTAG frequency
+	adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reset clock is MSI (4 MHz)
+	adapter speed 500
+}
+
+$_TARGETNAME configure -event examine-end {
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE004203C 0x00001800 0
+}
+
+$_TARGETNAME configure -event trace-config {
+	# nothing to do
+}
diff --git a/tcl/target/stm8l.cfg b/tcl/target/stm8l.cfg
index 5cc99e1..a06c4cb 100644
--- a/tcl/target/stm8l.cfg
+++ b/tcl/target/stm8l.cfg
@@ -4,7 +4,7 @@
 # stm8 devices support SWIM transports only.
 #
 
-transport select stlink_swim
+transport select swim
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -62,7 +62,7 @@ if { [info exists BLOCKSIZE] } {
    set _BLOCKSIZE 0x80
 }
 
-hla newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0
+swim newtap $_CHIPNAME cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
 
@@ -78,8 +78,10 @@ $_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocks
 # Set stm8l type
 $_TARGETNAME configure -enable_stm8l
 
-# The khz rate does not apply here, only slow <0> and fast <1>
-adapter_khz 1
+# Set high speed
+adapter speed 800
+# Set low speed
+#adapter speed 363
 
 reset_config srst_only
 
diff --git a/tcl/target/stm8s.cfg b/tcl/target/stm8s.cfg
index d55e61b..2dae655 100644
--- a/tcl/target/stm8s.cfg
+++ b/tcl/target/stm8s.cfg
@@ -4,7 +4,7 @@
 # stm8 devices support SWIM transports only.
 #
 
-transport select stlink_swim
+transport select swim
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -62,7 +62,7 @@ if { [info exists BLOCKSIZE] } {
    set _BLOCKSIZE 0x80
 }
 
-hla newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0
+swim newtap $_CHIPNAME cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
 
@@ -75,8 +75,10 @@ $_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocks
 # Uncomment this line to enable interrupts while instruction step
 #$_TARGETNAME configure -enable_step_irq
 
-# The khz rate does not apply here, only slow <0> and fast <1>
-adapter_khz 1
+# Set high speed
+adapter speed 800
+# Set low speed
+#adapter speed 363
 
 reset_config srst_only
 
diff --git a/tcl/target/stm8s103.cfg b/tcl/target/stm8s103.cfg
new file mode 100644
index 0000000..714acf4
--- /dev/null
+++ b/tcl/target/stm8s103.cfg
@@ -0,0 +1,13 @@
+#config script for STM8S103
+
+set FLASHEND 0x9FFF
+set EEPROMEND 0x427F
+set OPTIONEND 0x480A
+set BLOCKSIZE 0x40
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0x00
+   reset halt
+}
+
+source [find target/stm8s.cfg]
diff --git a/tcl/target/str710.cfg b/tcl/target/str710.cfg
index d26a8b1..29faaaa 100644
--- a/tcl/target/str710.cfg
+++ b/tcl/target/str710.cfg
@@ -1,5 +1,5 @@
 #start slow, speed up after reset
-adapter_khz 10
+adapter speed 10
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -29,9 +29,9 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_C
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
 
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
 $_TARGETNAME configure -event reset-init {
-	adapter_khz 6000
+	adapter speed 6000
 
 # Because the hardware cannot be interrogated for the protection state
 # of sectors, initialize all the sectors to be unprotected. The initial
diff --git a/tcl/target/str730.cfg b/tcl/target/str730.cfg
index 48d3134..e9e2f26 100644
--- a/tcl/target/str730.cfg
+++ b/tcl/target/str730.cfg
@@ -1,6 +1,6 @@
 #STR730 CPU
 
-adapter_khz 3000
+adapter speed 3000
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -27,15 +27,15 @@ reset_config trst_and_srst srst_pulls_trst
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
 
 #jtag nTRST and nSRST delay
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
 
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
 $_TARGETNAME configure -event reset-init {
-	adapter_khz 3000
+	adapter speed 3000
 
 # Because the hardware cannot be interrogated for the protection state
 # of sectors, initialize all the sectors to be unprotected. The initial
@@ -51,4 +51,3 @@ $_TARGETNAME configure -work-area-phys 0xA0000000 -work-area-size 0x4000 -work-a
 #flash bank <driver> <base> <size> <chip_width> <bus_width>
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME str7x 0x80000000 0x00040000 0 0 $_TARGETNAME STR73x
-
diff --git a/tcl/target/str750.cfg b/tcl/target/str750.cfg
index ef6e795..335d5ad 100644
--- a/tcl/target/str750.cfg
+++ b/tcl/target/str750.cfg
@@ -19,7 +19,7 @@ if { [info exists CPUTAPID] } {
 }
 
 # jtag speed
-adapter_khz 10
+adapter speed 10
 
 #use combined on interfaces or targets that can't set TRST/SRST separately
 reset_config trst_and_srst srst_pulls_trst
@@ -29,15 +29,15 @@ reset_config trst_and_srst srst_pulls_trst
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
 
 #jtag nTRST and nSRST delay
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
 
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
 $_TARGETNAME configure -event reset-init {
-	adapter_khz 3000
+	adapter speed 3000
 
 	init_smi
 # Because the hardware cannot be interrogated for the protection state
diff --git a/tcl/target/str912.cfg b/tcl/target/str912.cfg
index 36c0b2a..7426276 100644
--- a/tcl/target/str912.cfg
+++ b/tcl/target/str912.cfg
@@ -13,9 +13,9 @@ if { [info exists ENDIAN] } {
 }
 
 # jtag speed. We need to stick to 16kHz until we've finished reset.
-adapter_khz 16
+adapter speed 16
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 #use combined on interfaces or targets that can't set TRST/SRST separately
@@ -48,11 +48,11 @@ jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BST
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
 
-$_TARGETNAME configure -event reset-start { adapter_khz 16 }
+$_TARGETNAME configure -event reset-start { adapter speed 16 }
 
 $_TARGETNAME configure -event reset-init {
 	# We can increase speed now that we know the target is halted.
-	#adapter_khz 3000
+	#adapter speed 3000
 
 	# -- Enable 96K RAM
 	# PFQBC enabled / DTCM & AHB wait-states disabled
diff --git a/tcl/target/swm050.cfg b/tcl/target/swm050.cfg
index a819f9c..e6f2ecb 100644
--- a/tcl/target/swm050.cfg
+++ b/tcl/target/swm050.cfg
@@ -1,5 +1,7 @@
 # Synwit SWM050
 
+source [find target/swj-dp.tcl]
+
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
 } else {
@@ -16,10 +18,10 @@ if { [info exists WORKAREASIZE] } {
 if { [info exists CPUTAPID] } {
 	set _CPUTAPID $CPUTAPID
 } else {
-	set _CPUTAPID 0x410CC200
+	set _CPUTAPID 0x0bb11477
 }
 
-swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
@@ -27,6 +29,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
 
+adapter speed 1000
 
 $_TARGETNAME configure -event reset-init {
 	# Stop the watchdog, just to be safe
diff --git a/tcl/target/ti-cjtag.cfg b/tcl/target/ti-cjtag.cfg
index 7114b2a..7114b2a 100755..100644
--- a/tcl/target/ti-cjtag.cfg
+++ b/tcl/target/ti-cjtag.cfg
diff --git a/tcl/target/ti_calypso.cfg b/tcl/target/ti_calypso.cfg
index 9d3b293..52a84fb 100644
--- a/tcl/target/ti_calypso.cfg
+++ b/tcl/target/ti_calypso.cfg
@@ -32,7 +32,7 @@ if { [info exists WORKAREASIZE] } {
 	set _WORKAREASIZE 0x10000
 }
 
-adapter_khz 1000
+adapter speed 1000
 
 reset_config trst_and_srst
 
diff --git a/tcl/target/ti_cc26x0.cfg b/tcl/target/ti_cc26x0.cfg
index 7efecb6..f95d7b2 100644
--- a/tcl/target/ti_cc26x0.cfg
+++ b/tcl/target/ti_cc26x0.cfg
@@ -52,5 +52,4 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
 
-reset_config srst_only
-adapter_nsrst_delay 100
+cortex_m reset_config vectreset
diff --git a/tcl/target/ti_cc3220sf.cfg b/tcl/target/ti_cc3220sf.cfg
index f7d9bfe..74269aa 100644
--- a/tcl/target/ti_cc3220sf.cfg
+++ b/tcl/target/ti_cc3220sf.cfg
@@ -10,3 +10,31 @@ source [find target/ti_cc32xx.cfg]
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
+
+#
+# On CC32xx family of devices, sysreqreset is disabled, and vectreset is
+# blocked by the boot loader (stops in a while(1) statement). srst reset can
+# leave the target in a state that prevents debug. The following uses the
+# soft_reset_halt command to reset and halt the target. Then the PC and stack
+# are initialized from internal flash. This allows for a more reliable reset,
+# but with two caveats: it only works for the SF variant that has internal
+# flash, and it only resets the CPU and not any peripherals.
+#
+
+proc ocd_process_reset_inner { MODE } {
+
+	soft_reset_halt
+
+	# Initialize MSP, PSP, and PC from vector table at flash 0x01000800
+	mem2array boot 32 0x01000800 2
+
+	reg msp $boot(0)
+	reg psp $boot(0)
+	reg pc $boot(1)
+
+	if { 0 == [string compare $MODE run ] } {
+		resume
+	}
+
+	cc32xx.cpu invoke-event reset-end
+}
diff --git a/tcl/target/ti_cc32xx.cfg b/tcl/target/ti_cc32xx.cfg
index bc3038d..e3e3ebc 100644
--- a/tcl/target/ti_cc32xx.cfg
+++ b/tcl/target/ti_cc32xx.cfg
@@ -59,6 +59,3 @@ if { [info exists WORKAREASIZE] } {
 }
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-reset_config srst_only
-adapter_nsrst_delay 1100
diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg
index 4f8f523..91c0087 100644
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -98,8 +98,8 @@ $_TARGETNAME configure \
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg
index 0db83db..8b52746 100644
--- a/tcl/target/ti_dm365.cfg
+++ b/tcl/target/ti_dm365.cfg
@@ -90,8 +90,8 @@ $_TARGETNAME configure \
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg
index fa1e6e9..ccc650a 100644
--- a/tcl/target/ti_dm6446.cfg
+++ b/tcl/target/ti_dm6446.cfg
@@ -70,8 +70,8 @@ $_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
diff --git a/tcl/target/ti_msp432.cfg b/tcl/target/ti_msp432.cfg
index 3407f75..77f81da 100644
--- a/tcl/target/ti_msp432.cfg
+++ b/tcl/target/ti_msp432.cfg
@@ -42,10 +42,10 @@ if { [info exists WORKAREASIZE] } {
 	set _WORKAREASIZE 0x4000
 }
 
+
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
 
-reset_config srst_only
-adapter_nsrst_delay 100
+cortex_m reset_config sysresetreq
diff --git a/tcl/target/ti_tms570.cfg b/tcl/target/ti_tms570.cfg
index ce3a176..d06ff97 100644
--- a/tcl/target/ti_tms570.cfg
+++ b/tcl/target/ti_tms570.cfg
@@ -1,4 +1,4 @@
-adapter_khz 1500
+adapter speed 1500
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/tmpa900.cfg b/tcl/target/tmpa900.cfg
index 3ba3591..8e70700 100644
--- a/tcl/target/tmpa900.cfg
+++ b/tcl/target/tmpa900.cfg
@@ -28,7 +28,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
 
 #use combined on interfaces or targets that can't set TRST/SRST separately
 reset_config trst_and_srst
-adapter_nsrst_delay 20
+adapter srst delay 20
 jtag_ntrst_delay 20
 
 ######################
diff --git a/tcl/target/tmpa910.cfg b/tcl/target/tmpa910.cfg
index 5d41c8c..d933c0b 100644
--- a/tcl/target/tmpa910.cfg
+++ b/tcl/target/tmpa910.cfg
@@ -28,7 +28,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
 
 #use combined on interfaces or targets that can't set TRST/SRST separately
 reset_config trst_and_srst
-adapter_nsrst_delay 20
+adapter srst delay 20
 jtag_ntrst_delay 20
 
 ######################
diff --git a/tcl/target/tnetc4401.cfg b/tcl/target/tnetc4401.cfg
new file mode 100644
index 0000000..48f7545
--- /dev/null
+++ b/tcl/target/tnetc4401.cfg
@@ -0,0 +1,17 @@
+# Texas Instruments (TI) TNETC4401, MIPS32 DOCSIS-tailored SoC (4Kc-based)
+# Used in Knovative KC-100 and Motorola Surfboard SB5120 cable modems.
+# Datasheet: https://brezn.muc.ccc.de/~mazzoo/DOCSIS/tnetc4401.pdf
+transport select jtag
+set _TARGETNAME tnetc4401
+set _CPUTAPID 0x0000100f
+jtag newtap $_TARGETNAME tap -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id $_CPUTAPID
+target create $_TARGETNAME mips_m4k -chain-position $_TARGETNAME.tap -endian big
+
+# May need to halt manually before calling reset init
+$_TARGETNAME configure -event reset-init {
+	halt
+	echo "Attempting to disable watchdog..."
+	mwb phys 0xa8610b00 0 256
+	halt
+	wait_halt
+}
diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg
index 7ff3929..36e0db7 100644
--- a/tcl/target/u8500.cfg
+++ b/tcl/target/u8500.cfg
@@ -1,6 +1,6 @@
 #  Copyright (C) ST-Ericsson SA 2011
 #  Author : michel.jaouen@stericsson.com
-#  U8500 target 
+#  U8500 target
 
 proc mmu_off {} {
 	set cp [arm mrc 15 0 1 0 0]
@@ -31,7 +31,7 @@ proc ocd_gdb_restart {target_id} {
 proc smp_reg {} {
 	global _TARGETNAME_1
     global _TARGETNAME_2
-    targets $_TARGETNAME_1 
+    targets $_TARGETNAME_1
 	echo "$_TARGETNAME_1"
 	set pc1 [reg pc]
 	set stck1 [reg sp_svc]
@@ -68,7 +68,7 @@ proc pwrsts { } {
 		8 {
 			echo "A9 100% DVFS"
 		  }
-		c { 
+		c {
 			echo "A9 50% DVFS"
 		}
 	}
@@ -144,7 +144,7 @@ tcl_port 5555
 telnet_port 4444
 gdb_port 3333
 
-if { [info exists CHIPNAME] } {	
+if { [info exists CHIPNAME] } {
 global _CHIPNAME
     set _CHIPNAME $CHIPNAME
 } else {
@@ -194,12 +194,12 @@ set _TARGETNAME_1 $TARGETNAME_1
 if { [info exists DAP_DBG1] } {
 	set _DAP_DBG1 $DAP_DBG1
 } else {
-	set _DAP_DBG1 0x801A8000 
+	set _DAP_DBG1 0x801A8000
 }
 if { [info exists DAP_DBG2] } {
 	set _DAP_DBG2 $DAP_DBG2
 } else {
-	set _DAP_DBG2 0x801AA000 
+	set _DAP_DBG2 0x801AA000
 }
 
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
@@ -226,7 +226,7 @@ global _SMP
 set _SMP $SMP
 }
 global SMP
-if { $_SMP == 1} { 
+if { $_SMP == 1} {
 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
 }
 
@@ -264,7 +264,7 @@ proc att { } {
 	} else {
 		echo "target secured"
 	}
-	
+
 }
 
 
@@ -310,11 +310,11 @@ if {![info exists MAXSPEED]} {
 global _MAXSPEED
 set _MAXSPEED 15000
 } else {
-global _MAXSPEED 
+global _MAXSPEED
 set _MAXSPEED $MAXSPEED
 }
-global _MAXSPEED 
-adapter_khz $_MAXSPEED
+global _MAXSPEED
+adapter speed $_MAXSPEED
 
 
 gdb_breakpoint_override hard
@@ -322,5 +322,3 @@ set mem inaccessible-by-default-off
 
 jtag_ntrst_delay 100
 reset_config trst_and_srst combined
-
-
diff --git a/tcl/target/vybrid_vf6xx.cfg b/tcl/target/vybrid_vf6xx.cfg
index 7cb916d..c888d25 100644
--- a/tcl/target/vybrid_vf6xx.cfg
+++ b/tcl/target/vybrid_vf6xx.cfg
@@ -34,4 +34,4 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 set _TARGETNAME $_CHIPNAME.cpu
 target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap -dbgbase 0xc0088000
 target create ${_TARGETNAME}1 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/target/xmc1xxx.cfg b/tcl/target/xmc1xxx.cfg
index e693b59..eb94d7b 100644
--- a/tcl/target/xmc1xxx.cfg
+++ b/tcl/target/xmc1xxx.cfg
@@ -38,4 +38,4 @@ $_TARGETNAME configure -work-area-phys 0x20000000 \
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME xmc1xxx 0x10000000 0 0 0 $_TARGETNAME
 
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/target/xmc4xxx.cfg b/tcl/target/xmc4xxx.cfg
index e106d34..3020b28 100644
--- a/tcl/target/xmc4xxx.cfg
+++ b/tcl/target/xmc4xxx.cfg
@@ -57,4 +57,4 @@ if { ![using_hla] } {
 	cortex_m reset_config sysresetreq
 }
 
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/target/zynq_7000.cfg b/tcl/target/zynq_7000.cfg
index 1562768..b4b6f9f 100644
--- a/tcl/target/zynq_7000.cfg
+++ b/tcl/target/zynq_7000.cfg
@@ -23,7 +23,7 @@ target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap \
     -coreid 1 -dbgbase 0x80092000
 target smp ${_TARGETNAME}0 ${_TARGETNAME}1
 
-adapter_khz 1000
+adapter speed 1000
 
 ${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
 ${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"