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authorAndreas Färber <afaerber@suse.de>2016-05-14 20:21:49 +0200
committerFreddie Chopin <freddie.chopin@gmail.com>2016-05-20 21:38:03 +0100
commit0c8ec7c826c60391034fe5f0ea90f8538ac94b38 (patch)
tree3f1bf74454812f49bf5f2994a6eddc41677c99d8 /tcl/target
parentf630fac2e72af502d12139fdc864a01a4da7c868 (diff)
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Fix spelling of ARM Cortex
It's Cortex-Xn, not Cortex Xn or cortex xn or cortex-xn or CORTEX-Xn or CortexXn. Further it's Cortex-M0+, not M0plus. Cf. http://www.arm.com/products/processors/index.php Consistently write it the official way, so that it stops propagating. Originally spotted in the documentation, it mainly affects code comments but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output. Found via: git grep -i "Cortex " git grep -i "Cortex-" | grep -v "Cortex-" | grep -v ".cpu" git grep -i "CortexM" Change-Id: Ic7b6ca85253e027f6f0f751c628d1a2a391fe914 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3483 Tested-by: jenkins Reviewed-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Diffstat (limited to 'tcl/target')
-rw-r--r--tcl/target/altera_fpgasoc.cfg4
-rw-r--r--tcl/target/am335x.cfg4
-rw-r--r--tcl/target/am437x.cfg2
-rw-r--r--tcl/target/amdm37x.cfg2
-rw-r--r--tcl/target/at91sam3XXX.cfg2
-rw-r--r--tcl/target/at91sam3ax_xx.cfg2
-rw-r--r--tcl/target/at91sam3sXX.cfg2
-rw-r--r--tcl/target/at91sam3uxx.cfg2
-rw-r--r--tcl/target/at91sam4XXX.cfg2
-rw-r--r--tcl/target/at91sam4lXX.cfg2
-rw-r--r--tcl/target/at91sam4sXX.cfg2
-rw-r--r--tcl/target/at91sam4sd32x.cfg2
-rw-r--r--tcl/target/at91samdXX.cfg2
-rw-r--r--tcl/target/at91samg5x.cfg2
-rw-r--r--tcl/target/bcm281xx.cfg2
-rwxr-xr-xtcl/target/cc26xx.cfg2
-rwxr-xr-xtcl/target/cc32xx.cfg2
-rw-r--r--tcl/target/fm3.cfg2
-rw-r--r--tcl/target/imx51.cfg2
-rw-r--r--tcl/target/imx53.cfg2
-rw-r--r--tcl/target/imx6.cfg2
-rw-r--r--tcl/target/lpc1xxx.cfg10
-rw-r--r--tcl/target/nrf51.cfg2
-rw-r--r--tcl/target/omap3530.cfg2
-rw-r--r--tcl/target/stm32w108xx.cfg2
-rw-r--r--tcl/target/ti_tms570.cfg2
26 files changed, 32 insertions, 32 deletions
diff --git a/tcl/target/altera_fpgasoc.cfg b/tcl/target/altera_fpgasoc.cfg
index fccf8c5..25fe1f4 100644
--- a/tcl/target/altera_fpgasoc.cfg
+++ b/tcl/target/altera_fpgasoc.cfg
@@ -27,7 +27,7 @@ jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-
#
-# Cortex A9 target
+# Cortex-A9 target
#
# GDB target: Cortex-A9, using DAP, configuring only one core
@@ -59,6 +59,6 @@ $_TARGETNAME1 configure -event gdb-attach { halt }
#$_TARGETNAME2 configure -event gdb-attach { halt }
proc cycv_dbginit {target} {
- # General Cortex A8/A9 debug initialisation
+ # General Cortex-A8/A9 debug initialisation
cortex_a dbginit
}
diff --git a/tcl/target/am335x.cfg b/tcl/target/am335x.cfg
index ce7cfb6..7409615 100644
--- a/tcl/target/am335x.cfg
+++ b/tcl/target/am335x.cfg
@@ -63,13 +63,13 @@ proc enable_default_taps { taps } {
}
#
-# Cortex M3 target
+# Cortex-M3 target
#
set _TARGETNAME_2 $_CHIPNAME.m3
target create $_TARGETNAME_2 cortex_m -chain-position $_CHIPNAME.m3_dap
#
-# Cortex A8 target
+# Cortex-A8 target
#
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
diff --git a/tcl/target/am437x.cfg b/tcl/target/am437x.cfg
index 4f97f81..fe0ffff 100644
--- a/tcl/target/am437x.cfg
+++ b/tcl/target/am437x.cfg
@@ -484,7 +484,7 @@ jtag configure $JRC_NAME -event setup "jtag tapenable $DEBUGSS_NAME"
jtag configure $JRC_NAME -event post-reset "runtest 100"
#
-# Cortex A9 target
+# Cortex-A9 target
#
target create $_TARGETNAME cortex_a -chain-position $DEBUGSS_NAME -coreid 0 -dbgbase 0x80000000
diff --git a/tcl/target/amdm37x.cfg b/tcl/target/amdm37x.cfg
index 59fbbf0..c00dae9 100644
--- a/tcl/target/amdm37x.cfg
+++ b/tcl/target/amdm37x.cfg
@@ -199,7 +199,7 @@ $_TARGETNAME configure -event gdb-attach {
# Run this to enable invasive debugging. This is run automatically in the
# reset sequence.
proc amdm37x_dbginit {target} {
- # General Cortex A8 debug initialisation
+ # General Cortex-A8 debug initialisation
cortex_a dbginit
# Enable DBGEN signal. This signal is described in the ARM v7 TRM, but
diff --git a/tcl/target/at91sam3XXX.cfg b/tcl/target/at91sam3XXX.cfg
index 6af1f5c..fca655d 100644
--- a/tcl/target/at91sam3XXX.cfg
+++ b/tcl/target/at91sam3XXX.cfg
@@ -1,4 +1,4 @@
-# script for ATMEL sam3, a CORTEX-M3 chip
+# script for ATMEL sam3, a Cortex-M3 chip
#
# at91sam3u4e
# at91sam3u2e
diff --git a/tcl/target/at91sam3ax_xx.cfg b/tcl/target/at91sam3ax_xx.cfg
index 8e6bc33..e561771 100644
--- a/tcl/target/at91sam3ax_xx.cfg
+++ b/tcl/target/at91sam3ax_xx.cfg
@@ -1,4 +1,4 @@
-# script for ATMEL sam3, a CORTEX-M3 chip
+# script for ATMEL sam3, a Cortex-M3 chip
#
# at91sam3A4C
# at91sam3A8C
diff --git a/tcl/target/at91sam3sXX.cfg b/tcl/target/at91sam3sXX.cfg
index ca7092b..09146bd 100644
--- a/tcl/target/at91sam3sXX.cfg
+++ b/tcl/target/at91sam3sXX.cfg
@@ -1,4 +1,4 @@
-# script for ATMEL sam3, a CORTEX-M3 chip
+# script for ATMEL sam3, a Cortex-M3 chip
#
# at91sam3s4c
# at91sam3s4b
diff --git a/tcl/target/at91sam3uxx.cfg b/tcl/target/at91sam3uxx.cfg
index a11afc0..b42ae19 100644
--- a/tcl/target/at91sam3uxx.cfg
+++ b/tcl/target/at91sam3uxx.cfg
@@ -1,4 +1,4 @@
-# script for ATMEL sam3, a CORTEX-M3 chip
+# script for ATMEL sam3, a Cortex-M3 chip
#
# at91sam3u4e
# at91sam3u2e
diff --git a/tcl/target/at91sam4XXX.cfg b/tcl/target/at91sam4XXX.cfg
index 8f32ca0..ca80143 100644
--- a/tcl/target/at91sam4XXX.cfg
+++ b/tcl/target/at91sam4XXX.cfg
@@ -1,5 +1,5 @@
#
-# script for ATMEL sam4, a CORTEX-M4 chip
+# script for ATMEL sam4, a Cortex-M4 chip
#
#
diff --git a/tcl/target/at91sam4lXX.cfg b/tcl/target/at91sam4lXX.cfg
index 46c38ae..4aee7d0 100644
--- a/tcl/target/at91sam4lXX.cfg
+++ b/tcl/target/at91sam4lXX.cfg
@@ -1,4 +1,4 @@
-# script for ATMEL sam4l, a CORTEX-M4 chip
+# script for ATMEL sam4l, a Cortex-M4 chip
#
source [find target/at91sam4XXX.cfg]
diff --git a/tcl/target/at91sam4sXX.cfg b/tcl/target/at91sam4sXX.cfg
index 3de4aa8..8883e23 100644
--- a/tcl/target/at91sam4sXX.cfg
+++ b/tcl/target/at91sam4sXX.cfg
@@ -1,4 +1,4 @@
-# script for ATMEL sam4, a CORTEX-M4 chip
+# script for ATMEL sam4, a Cortex-M4 chip
#
source [find target/at91sam4XXX.cfg]
diff --git a/tcl/target/at91sam4sd32x.cfg b/tcl/target/at91sam4sd32x.cfg
index e44db66..077b1f5 100644
--- a/tcl/target/at91sam4sd32x.cfg
+++ b/tcl/target/at91sam4sd32x.cfg
@@ -1,4 +1,4 @@
-# script for ATMEL sam4sd32, a CORTEX-M4 chip
+# script for ATMEL sam4sd32, a Cortex-M4 chip
#
source [find target/at91sam4XXX.cfg]
diff --git a/tcl/target/at91samdXX.cfg b/tcl/target/at91samdXX.cfg
index 50d93f5..47b4f5f 100644
--- a/tcl/target/at91samdXX.cfg
+++ b/tcl/target/at91samdXX.cfg
@@ -1,5 +1,5 @@
#
-# script for Atmel SAMD, SAMR, SAML or SAMC, a CORTEX-M0 chip
+# script for Atmel SAMD, SAMR, SAML or SAMC, a Cortex-M0 chip
#
#
diff --git a/tcl/target/at91samg5x.cfg b/tcl/target/at91samg5x.cfg
index d26455b..57274c0 100644
--- a/tcl/target/at91samg5x.cfg
+++ b/tcl/target/at91samg5x.cfg
@@ -1,4 +1,4 @@
-# script for the ATMEL samg5x CORTEX-M4F chip family
+# script for the ATMEL samg5x Cortex-M4F chip family
#
source [find target/at91sam4XXX.cfg]
diff --git a/tcl/target/bcm281xx.cfg b/tcl/target/bcm281xx.cfg
index c05682f..224af79 100644
--- a/tcl/target/bcm281xx.cfg
+++ b/tcl/target/bcm281xx.cfg
@@ -17,7 +17,7 @@ if { [info exists DAP_TAPID] } {
jtag newtap $_CHIPNAME dap -expected-id $_DAP_TAPID -irlen 4
-# Dual Cortex A9s
+# Dual Cortex-A9
set _TARGETNAME0 $_CHIPNAME.cpu0
set _TARGETNAME1 $_CHIPNAME.cpu1
diff --git a/tcl/target/cc26xx.cfg b/tcl/target/cc26xx.cfg
index 0fa4600..1492e6a 100755
--- a/tcl/target/cc26xx.cfg
+++ b/tcl/target/cc26xx.cfg
@@ -37,7 +37,7 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc"
#
-# Cortex M3 target
+# Cortex-M3 target
#
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap
diff --git a/tcl/target/cc32xx.cfg b/tcl/target/cc32xx.cfg
index ff65450..154bf91 100755
--- a/tcl/target/cc32xx.cfg
+++ b/tcl/target/cc32xx.cfg
@@ -47,7 +47,7 @@ if {[using_jtag]} {
}
#
-# Cortex M3 target
+# Cortex-M3 target
#
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap
diff --git a/tcl/target/fm3.cfg b/tcl/target/fm3.cfg
index e2d78d1..78bbc94 100644
--- a/tcl/target/fm3.cfg
+++ b/tcl/target/fm3.cfg
@@ -27,7 +27,7 @@ if {[using_jtag]} {
jtag_ntrst_delay 100
}
-# Fujitsu cortex-M3 reset configuration
+# Fujitsu Cortex-M3 reset configuration
reset_config trst_only
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
diff --git a/tcl/target/imx51.cfg b/tcl/target/imx51.cfg
index 15d5c04..b143aad 100644
--- a/tcl/target/imx51.cfg
+++ b/tcl/target/imx51.cfg
@@ -40,7 +40,7 @@ jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
proc imx51_dbginit {target} {
- # General Cortex A8 debug initialisation
+ # General Cortex-A8 debug initialisation
cortex_a dbginit
}
diff --git a/tcl/target/imx53.cfg b/tcl/target/imx53.cfg
index e77bc34..87a3008 100644
--- a/tcl/target/imx53.cfg
+++ b/tcl/target/imx53.cfg
@@ -40,7 +40,7 @@ jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
proc imx53_dbginit {target} {
- # General Cortex A8 debug initialisation
+ # General Cortex-A8 debug initialisation
cortex_a dbginit
}
diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg
index 11c2134..4f7e98a 100644
--- a/tcl/target/imx6.cfg
+++ b/tcl/target/imx6.cfg
@@ -47,7 +47,7 @@ target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
proc imx6_dbginit {target} {
- # General Cortex A8/A9 debug initialisation
+ # General Cortex-A8/A9 debug initialisation
cortex_a dbginit
}
diff --git a/tcl/target/lpc1xxx.cfg b/tcl/target/lpc1xxx.cfg
index 226425d..9c10e9f 100644
--- a/tcl/target/lpc1xxx.cfg
+++ b/tcl/target/lpc1xxx.cfg
@@ -56,7 +56,7 @@ if { [info exists CPUTAPID] } {
# Allow user override
set _CPUTAPID $CPUTAPID
} else {
- # LPC8xx/LPC11xx/LPC12xx use a Cortex M0/M0+ core, LPC13xx/LPC17xx use a Cortex M3 core,LPC40xx use a Cortex-M4F core.
+ # LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core.
if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
set _CPUTAPID 0x0bb11477
} elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
@@ -148,10 +148,10 @@ if {[using_jtag]} {
jtag_ntrst_delay 200
}
-# LPC8xx (Cortex M0+ core) support SYSRESETREQ
-# LPC11xx/LPC12xx (Cortex M0 core) support SYSRESETREQ
-# LPC13xx/LPC17xx (Cortex M3 core) support SYSRESETREQ
-# LPC40xx (Cortex M4F core) support SYSRESETREQ
+# LPC8xx (Cortex-M0+ core) support SYSRESETREQ
+# LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ
+# LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ
+# LPC40xx (Cortex-M4F core) support SYSRESETREQ
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg
index 0768120..280dd4f 100644
--- a/tcl/target/nrf51.cfg
+++ b/tcl/target/nrf51.cfg
@@ -1,5 +1,5 @@
#
-# script for Nordic nRF51 series, a CORTEX-M0 chip
+# script for Nordic nRF51 series, a Cortex-M0 chip
#
source [find target/swj-dp.tcl]
diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index f9dcf7c..c2929d1 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -53,7 +53,7 @@ jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
proc omap3_dbginit {target} {
- # General Cortex A8 debug initialisation
+ # General Cortex-A8 debug initialisation
cortex_a dbginit
# Enable DBGU signal for OMAP353x
$target mww phys 0x5401d030 0x00002000
diff --git a/tcl/target/stm32w108xx.cfg b/tcl/target/stm32w108xx.cfg
index 1a19135..d07afc4 100644
--- a/tcl/target/stm32w108xx.cfg
+++ b/tcl/target/stm32w108xx.cfg
@@ -1,7 +1,7 @@
#
# Target configuration for the ST STM32W108xx chips
#
-# Processor: ARM Cortex M3
+# Processor: ARM Cortex-M3
# Date: 2013-06-09
# Author: Giuseppe Barba <giuseppe.barba@gmail.com>
diff --git a/tcl/target/ti_tms570.cfg b/tcl/target/ti_tms570.cfg
index 582a4bf..21da6c0 100644
--- a/tcl/target/ti_tms570.cfg
+++ b/tcl/target/ti_tms570.cfg
@@ -53,7 +53,7 @@ jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
-# Cortex R4 target
+# Cortex-R4 target
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \
-chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003
generated by cgit v1.1 at 2024-11-17 02:39:44 +0000