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| author | Edward Fewell <efewell@ti.com> | 2017-12-28 17:38:21 -0600 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2018-06-06 15:38:25 +0100 |
| commit | d02de3a8a92091b9761ebaf44dff1a71f5b2edcb (patch) | |
| tree | 0408c6c8a71634ea39bf3b5cb872274cfab64634 /tcl/target/ti_cc32xx.cfg | |
| parent | a077715b71dbe2e02561c3e33d15a0f8bc9be19a (diff) | |
| download | riscv-openocd-d02de3a8a92091b9761ebaf44dff1a71f5b2edcb.zip riscv-openocd-d02de3a8a92091b9761ebaf44dff1a71f5b2edcb.tar.gz riscv-openocd-d02de3a8a92091b9761ebaf44dff1a71f5b2edcb.tar.bz2 | |
flash/nor: Add support for TI CC3220SF internal flash
Added cc3220sf flash driver to support the TI CC3220SF
microcontrollers. Implemented flash driver to support the
internal flash of the CC3220SF. The implementation does not
support the serial flash of the CC32xx family that requires
connection over UART, and not via JTAG/SWD debug. Added config
files for both CC32xx devices (no flash) and CC3220SF (with
flash).
Updated to implement comments from code review.
Additional updates to handle remaining comments from review.
Additional updates per review.
Added code to only request aligned writes and full 32-bit
words down to flash helper algorithm. Updated for recent
changes in OpenOCD flash code.
Removed cc32xx.cfg file made obsolete by this patch.
Change-Id: I58fc1478d07238d39c7ef02339f1097a91668c47
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/4319
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'tcl/target/ti_cc32xx.cfg')
| -rw-r--r-- | tcl/target/ti_cc32xx.cfg | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/tcl/target/ti_cc32xx.cfg b/tcl/target/ti_cc32xx.cfg new file mode 100644 index 0000000..bc3038d --- /dev/null +++ b/tcl/target/ti_cc32xx.cfg @@ -0,0 +1,64 @@ +# +# Texas Instruments CC32xx - ARM Cortex-M4 +# +# http://www.ti.com/product/CC3200 +# http://www.ti.com/product/CC3220 +# + +source [find target/swj-dp.tcl] +source [find target/icepick.cfg] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cc32xx +} + +# +# Main DAP +# +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + if {[using_jtag]} { + set _DAP_TAPID 0x4BA00477 + } else { + set _DAP_TAPID 0x2BA01477 + } +} + +if {[using_jtag]} { + jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable + jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0" +} else { + swj_newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID +} + +# +# ICEpick-C (JTAG route controller) +# +if { [info exists JRC_TAPID] } { + set _JRC_TAPID $JRC_TAPID +} else { + set _JRC_TAPID 0x0B97C02F +} + +if {[using_jtag]} { + jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version + jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu" +} + +set _TARGETNAME $_CHIPNAME.cpu +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x2000 +} + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +reset_config srst_only +adapter_nsrst_delay 1100 |