Flash driver for STM32G0xx and STM32G4xx

Flash module of STM32G0/G4 family is quite similar to the one of
STM32L4, so only minor changes are required, in particular
adaption of flash loader to Cortex-M0. Register addresses
passed to flash loader to simplify integration of L5.
Added re-probe after option byte load.
Added flash size override via cfg file.
WRPxxR mask now based on max. number of pages instead of fixed 0xFF,
as G4 devices fill up unused bits with '1'.
Sizes in stm32l4_probe changed to multiples of 1kB.

Tested with Nucleo-G071RB, G030J6, Nucleo-G431RB and Nucleo-G474RE.
Gap handling in G4 Cat. 3 dual bank mode tested with STM32G473RB.
This handling isn't optimal as the bank size includes the
size of the gap. WB not tested.

Change-Id: I24df7c065afeb71c11c7e96de4aa9fdb91845593
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4807
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

1 files changed, 88 insertions, 0 deletions

diff --git a/tcl/target/stm32g0x.cfg b/tcl/target/stm32g0x.cfg
new file mode 100644
index 0000000..50836ea
--- /dev/null
+++ b/tcl/target/stm32g0x.cfg
@@ -0,0 +1,88 @@
+# script for stm32g0x family
+
+#
+# stm32g0 devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32g0x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# Smallest proposed target has 8kB ram, use 4kB by default to avoid surprises
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x1000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	# Section 37.5.5 - corresponds to Cortex-M0+
+	set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+# reasonable default
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+proc stm32g0x_default_reset_start {} {
+	# Reset clock is HSI16 (16 MHz)
+	adapter speed 2000
+}
+
+proc stm32g0x_default_examine_end {} {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+	mmw 0x40015804 0x00000006 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0x40015808 0x00001800 0
+}
+
+proc stm32g0x_default_reset_init {} {
+	# Increase clock to 64 Mhz
+	mmw 0x40022000 0x00000002 0x00000005	;# FLASH_ACR: Latency = 2
+	mww 0x4002100C 0x30000802				;# RCC_PLLCFGR = PLLR=/2, PLLN=8, PLLM=/1, PLLSRC=0x2
+	mmw 0x40021000 0x01000000 0x00000000	;# RCC_CR |= PLLON
+	mmw 0x40021008 0x00000002 0x00000005	;# RCC_CFGR: SW=PLLRCLK
+
+	# Boost JTAG frequency
+	adapter speed 4000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32g0x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32g0x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32g0x_default_reset_init }