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| author | Spencer Oliver <spen@spen-soft.co.uk> | 2013-08-06 13:12:10 +0100 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2014-01-09 15:22:42 +0000 |
| commit | acc4bb83fd1f26a677fdc2c8ccdc7a235f877d2d (patch) | |
| tree | 4a8ac63e67ef83e7514dc25e05b73b39c5f81cc0 /tcl/target/stm32f1x.cfg | |
| parent | 4dc8cd201c667bac72bc083ef1fa1b285eb093fc (diff) | |
| download | riscv-openocd-acc4bb83fd1f26a677fdc2c8ccdc7a235f877d2d.zip riscv-openocd-acc4bb83fd1f26a677fdc2c8ccdc7a235f877d2d.tar.gz riscv-openocd-acc4bb83fd1f26a677fdc2c8ccdc7a235f877d2d.tar.bz2 | |
cfg: add stm32 cmsis-dap compliant config
Change-Id: I3cfb21fdcef830e22b03bf4b5d58993728cc7475
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1543
Tested-by: jenkins
Diffstat (limited to 'tcl/target/stm32f1x.cfg')
| -rw-r--r-- | tcl/target/stm32f1x.cfg | 28 |
1 files changed, 19 insertions, 9 deletions
diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg index 12d33d5..f32654a 100644 --- a/tcl/target/stm32f1x.cfg +++ b/tcl/target/stm32f1x.cfg @@ -1,5 +1,10 @@ # script for stm32f1x family +# +# stm32 devices support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] + if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { @@ -20,12 +25,6 @@ if { [info exists WORKAREASIZE] } { set _WORKAREASIZE 0x1000 } -# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz -adapter_khz 1000 - -adapter_nsrst_delay 100 -jtag_ntrst_delay 100 - #jtag scan chain if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID @@ -34,7 +33,8 @@ if { [info exists CPUTAPID] } { # Section 26.6.3 set _CPUTAPID 0x3ba00477 } -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID if { [info exists BSTAPID] } { # FIXME this never gets used to override defaults... @@ -59,13 +59,15 @@ if { [info exists BSTAPID] } { set _BSTAPID8 0x06420041 # VL line devices, Rev A set _BSTAPID9 0x06428041 - } -jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ + +if {$using_jtag} { + jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \ -expected-id $_BSTAPID6 -expected-id $_BSTAPID7 \ -expected-id $_BSTAPID8 -expected-id $_BSTAPID9 +} set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME @@ -76,6 +78,14 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +adapter_khz 1000 + +adapter_nsrst_delay 100 +if {$using_jtag} { + jtag_ntrst_delay 100 +} + # if srst is not fitted use SYSRESETREQ to # perform a soft reset cortex_m reset_config sysresetreq |