diff options
| author | micbis <michele.bisogno.ct@renesas.com> | 2022-05-10 10:49:31 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2022-05-21 09:01:13 +0000 |
| commit | 19e992e8827a13a9507b64b3a96895e6ed3d714a (patch) | |
| tree | b2d4979bbbd521daaeb3616289934a55d7784f04 /tcl/target/renesas_rz_g2.cfg | |
| parent | 631d0bddfaadac63a7d8ff3ef916614d62c86b1e (diff) | |
| download | riscv-openocd-19e992e8827a13a9507b64b3a96895e6ed3d714a.zip riscv-openocd-19e992e8827a13a9507b64b3a96895e6ed3d714a.tar.gz riscv-openocd-19e992e8827a13a9507b64b3a96895e6ed3d714a.tar.bz2 | |
tcl/target/renesas_rz_g2: Added RZ/G2LC and RZ/G2UL
Added support for two new devices: RZ/G2LC and RZ/G2UL
Change-Id: Iec6ba88c1d279f50808b060343b45c796bbfdbfc
Signed-off-by: micbis <michele.bisogno.ct@renesas.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6972
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'tcl/target/renesas_rz_g2.cfg')
| -rw-r--r-- | tcl/target/renesas_rz_g2.cfg | 28 |
1 files changed, 22 insertions, 6 deletions
diff --git a/tcl/target/renesas_rz_g2.cfg b/tcl/target/renesas_rz_g2.cfg index 3615aa0..a3d5f48 100644 --- a/tcl/target/renesas_rz_g2.cfg +++ b/tcl/target/renesas_rz_g2.cfg @@ -6,11 +6,13 @@ # - Each SOC can boot through the Cortex-A5x cores # Supported RZ/G2 SOCs and their cores: -# RZ/G2H: Cortex-A57 x4, Cortex-A53 x4, Cortex-R7 -# RZ/G2M: Cortex-A57 x2, Cortex-A53 x4, Cortex-R7 -# RZ/G2N: Cortex-A57 x2, Cortex-R7 -# RZ/G2E: Cortex-A53 x2, Cortex-R7 -# RZ/G2L: Cortex-A55 x2, Cortex-M33 +# RZ/G2H: Cortex-A57 x4, Cortex-A53 x4, Cortex-R7 +# RZ/G2M: Cortex-A57 x2, Cortex-A53 x4, Cortex-R7 +# RZ/G2N: Cortex-A57 x2, Cortex-R7 +# RZ/G2E: Cortex-A53 x2, Cortex-R7 +# RZ/G2L: Cortex-A55 x2, Cortex-M33 +# RZ/G2LC: Cortex-A55 x2, Cortex-M33 +# RZ/G2UL: Cortex-A55 x1, Cortex-M33 # Usage: # There are 2 configuration options: @@ -75,6 +77,20 @@ switch $_soc { set _boot_core CA55 set _ap_num 0 } + G2LC { + set _CHIPNAME r9a07g044c + set _num_ca55 2 + set _num_cm33 1 + set _boot_core CA55 + set _ap_num 0 + } + G2UL { + set _CHIPNAME r9a07g043u + set _num_ca55 1 + set _num_cm33 1 + set _boot_core CA55 + set _ap_num 0 + } default { error "'$_soc' is invalid!" } @@ -169,7 +185,7 @@ if { $_boot_core == "CA57" } { echo "SMP targets:$smp_targets" eval "target smp $smp_targets" -if { $_soc == "G2L"} { +if { $_soc == "G2L" || $_soc == "G2LC" || $_soc == "G2UL" } { target create $_CHIPNAME.axi_ap mem_ap -dap $_DAPNAME -ap-num 1 } |