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| author | Sergio Chico <sergio.chico@gmail.com> | 2013-11-10 16:03:40 +0100 |
|---|---|---|
| committer | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2013-12-14 21:53:16 +0000 |
| commit | 93a3a82e49e7d1df855095dd541e9c04ad7823bc (patch) | |
| tree | a26d5939605b3c86bb3407bf683da241eb55757f /tcl/target/or1k.cfg | |
| parent | 2d64cf92aed12fc785afe8bd8bd759ae28a6b2eb (diff) | |
| download | riscv-openocd-93a3a82e49e7d1df855095dd541e9c04ad7823bc.zip riscv-openocd-93a3a82e49e7d1df855095dd541e9c04ad7823bc.tar.gz riscv-openocd-93a3a82e49e7d1df855095dd541e9c04ad7823bc.tar.bz2 | |
topic: Support for the Xilinx BSCAN_* Virtual JTAG in Openrisc
This add support to the Xilinx BSCAN_* virtual JTAG interface.
This is the Xilinx equivalent of the Altera sld_virtual_jtag interface,
it allows a user to connect to the debug unit through the main
FPGA JTAG connection.
Change-Id: Ia438e910650cff9cbc8f810b719fc1d5de5a8188
Signed-off-by: Sergio Chico <sergio.chico@gmail.com>
Reviewed-on: http://openocd.zylin.com/1806
Tested-by: jenkins
Reviewed-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'tcl/target/or1k.cfg')
| -rw-r--r-- | tcl/target/or1k.cfg | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/tcl/target/or1k.cfg b/tcl/target/or1k.cfg index 84514ef..acec700 100644 --- a/tcl/target/or1k.cfg +++ b/tcl/target/or1k.cfg @@ -29,6 +29,23 @@ if { [string compare $_TAP_TYPE "VJTAG"] == 0 } { # Select the TAP core we are using tap_select vjtag + +} elseif { [string compare $_TAP_TYPE "XILINX_BSCAN"] == 0 } { + + if { [info exists FPGATAPID] } { + set _FPGATAPID $FPGATAPID + } else { + puts "You need to set your FPGA JTAG ID" + shutdown + } + + jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_FPGATAPID + + set _TARGETNAME $_CHIPNAME.cpu + target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME + + # Select the TAP core we are using + tap_select xilinx_bscan } else { # OpenCores Mohor JTAG TAP ID set _CPUTAPID 0x14951185 |