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| author | Paul Fertser <fercerpav@gmail.com> | 2013-10-13 19:15:24 +0400 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2013-10-29 22:49:35 +0000 |
| commit | d4e195ad1b544b0396cab4c70437371958769196 (patch) | |
| tree | 610413e0cdd6d95d282b950e571913eeec5a7c4e /tcl/target/omap3530.cfg | |
| parent | 2b10052097c882cf0ed92748c15ff6ee001c1f8f (diff) | |
| download | riscv-openocd-d4e195ad1b544b0396cab4c70437371958769196.zip riscv-openocd-d4e195ad1b544b0396cab4c70437371958769196.tar.gz riscv-openocd-d4e195ad1b544b0396cab4c70437371958769196.tar.bz2 | |
Remove jtag_rclk from target configs
Some boards might have RCLK omitted from the JTAG connector and if the
interface claims support for it, OpenOCD will end up trying to use
RCLK while it's actually impossible.
This is a "cd tcl/target; sed -i s/jtag_rclk/adapter_khz/g *" patch.
Change-Id: Iee7337107bc1457966b104389ba9db75a9c860b4
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1695
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Mathias Küster <kesmtp@freenet.de>
Diffstat (limited to 'tcl/target/omap3530.cfg')
| -rw-r--r-- | tcl/target/omap3530.cfg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg index 0e20852..f9dcf7c 100644 --- a/tcl/target/omap3530.cfg +++ b/tcl/target/omap3530.cfg @@ -62,8 +62,8 @@ proc omap3_dbginit {target} { # be absolutely certain the JTAG clock will work with the worst-case # 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in. # OK to speed up *after* PLL and clock tree setup. -jtag_rclk 1000 -$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 } +adapter_khz 1000 +$_TARGETNAME configure -event "reset-start" { adapter_khz 1000 } # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset # ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick |