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| author | Paul Fertser <fercerpav@gmail.com> | 2013-09-28 14:23:15 +0400 |
|---|---|---|
| committer | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2014-08-11 21:25:56 +0000 |
| commit | c7384117c66e8f18896ca09ab8095d6da16bb1e5 (patch) | |
| tree | 2513a1c61d2d8c6d92171a238281189ca3962f4a /tcl/target/nrf51.cfg | |
| parent | f701c0cbeb346df4cda378d3b4d5136aabba3b37 (diff) | |
| download | riscv-openocd-c7384117c66e8f18896ca09ab8095d6da16bb1e5.zip riscv-openocd-c7384117c66e8f18896ca09ab8095d6da16bb1e5.tar.gz riscv-openocd-c7384117c66e8f18896ca09ab8095d6da16bb1e5.tar.bz2 | |
Allow transports to override the selected target (hla configs unification)
This should allow to share common configs for both regular access and
high-level adapters.
Use the newly-added functionality in stlink and icdi drivers, amend
the configs accordingly.
Runtime-tested with a TI tm4c123g board.
Change-Id: Ibb88266a4ca25f06f6c073e916c963f017447bad
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
[gus@projectgus.com: context-specific deprecation warnings]
Signed-off-by: Angus Gratton <gus@projectgus.com>
[andrew.smirnov@gmail.com: additional nrf51.cfg mods]
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Tested-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Reviewed-on: http://openocd.zylin.com/1664
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Diffstat (limited to 'tcl/target/nrf51.cfg')
| -rw-r--r-- | tcl/target/nrf51.cfg | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg new file mode 100644 index 0000000..abb46fd --- /dev/null +++ b/tcl/target/nrf51.cfg @@ -0,0 +1,52 @@ +# +# script for Nordic nRF51 series, a CORTEX-M0 chip +# + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME nrf51 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 2kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x800 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0bb11477 +} + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +if {![using_hla]} { + # The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal + cortex_m reset_config sysresetreq +} + +flash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME +flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME + +# +# The chip should start up from internal 16Mhz RC, so setting adapter +# clock to 1Mhz should be OK +# +adapter_khz 1000 |