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| author | Paul Fertser <fercerpav@gmail.com> | 2014-02-21 15:28:49 +0400 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2014-03-29 08:07:16 +0000 |
| commit | de9ebc5ce6432830d473aba769c34ae38794c947 (patch) | |
| tree | 9dfa930ff028b4ac77216f4a1dca5f1e0f19ffe6 /tcl/target/mdr32f9q2i.cfg | |
| parent | 0f566ae1a78b054328de2123ff36f93bc5b8fd93 (diff) | |
| download | riscv-openocd-de9ebc5ce6432830d473aba769c34ae38794c947.zip riscv-openocd-de9ebc5ce6432830d473aba769c34ae38794c947.tar.gz riscv-openocd-de9ebc5ce6432830d473aba769c34ae38794c947.tar.bz2 | |
tcl/target: make milandr configs swd-compatible
Change-Id: Ibb34f0d7829b205341bcce511ffc2624bdfe2c75
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1962
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'tcl/target/mdr32f9q2i.cfg')
| -rw-r--r-- | tcl/target/mdr32f9q2i.cfg | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/tcl/target/mdr32f9q2i.cfg b/tcl/target/mdr32f9q2i.cfg index a37ed8f..8e8262d 100644 --- a/tcl/target/mdr32f9q2i.cfg +++ b/tcl/target/mdr32f9q2i.cfg @@ -1,6 +1,8 @@ # MDR32F9Q2I (1986ВЕ92У) # http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=57&cntnt01returnid=68 +source [find target/swj-dp.tcl] + if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { @@ -20,19 +22,13 @@ if { [info exists WORKAREASIZE] } { set _WORKAREASIZE 0x8000 } -# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz -adapter_khz 1000 - -adapter_nsrst_delay 100 -jtag_ntrst_delay 100 - #jtag scan chain if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x4ba00477 } -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME @@ -46,6 +42,14 @@ if { [info exists IMEMORY] && [string equal $IMEMORY true] } { flash bank $_CHIPNAME.flash mdr 0x08000000 0x20000 0 0 $_TARGETNAME 0 32 4 } +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +adapter_khz 1000 + +adapter_nsrst_delay 100 +if {$using_jtag} { + jtag_ntrst_delay 100 +} + # if srst is not fitted use SYSRESETREQ to # perform a soft reset cortex_m reset_config sysresetreq |