David Brownell <david-b@pacbell.net>

Update the board config for the DaVinci DM355 EVM so the reset-init
event handler does the rest of the work it should do:

 - minor PLL setup bugfixes
 - initialize the DDR2 controller
 - probe both NAND banks
 - initialize UART0
 - enable the icache


git-svn-id: svn://svn.berlios.de/openocd/trunk@2699 b42882b7-edfa-0310-969c-e2dbd0fdcd60

1 files changed, 9 insertions, 1 deletions

diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg
index 07a26b2..658e7fe 100644
--- a/tcl/target/davinci.cfg
+++ b/tcl/target/davinci.cfg
@@ -125,6 +125,7 @@ proc pll_v02_setup {pll_addr mult config} {
 		set pllstat [expr $pll_addr + 0x013c]
 		while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
 	}
+	mww [expr $pll_addr + 0x0138] 0x00
 
 	# 11 - wait at least 5 usec for reset to finish
 	# (assume covered by overheads including JTAG messaging)
@@ -152,7 +153,14 @@ proc psc_enable {module} {
 	mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f
 }
 
-# execute non-DSP PSC transition(s) set up by psc_enable
+# prepare a non-DSP module to be reset; finish with psc_go
+proc psc_reset {module} {
+	set psc_addr 0x01c41000
+	# write MDCTL
+	mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x01 0x1f
+}
+
+# execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc
 proc psc_go {} {
 	set psc_addr 0x01c41000
 	set ptstat_addr [expr $psc_addr + 0x0128]