diff options
| author | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-06-25 14:51:18 +0300 |
|---|---|---|
| committer | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-06-25 14:51:18 +0300 |
| commit | 2eedd74197f12fb8c30f259207430713291e8ec0 (patch) | |
| tree | 8a27b3ebbdddb49c32477151bc66e339e84b46fe /tcl/target/c100helper.tcl | |
| parent | fdd07f127998f8669784fa64b67a43dea97c1837 (diff) | |
| parent | ad87fbd1cf28760795c4e18f3318a2d720e5a8a6 (diff) | |
| download | riscv-openocd-2eedd74197f12fb8c30f259207430713291e8ec0.zip riscv-openocd-2eedd74197f12fb8c30f259207430713291e8ec0.tar.gz riscv-openocd-2eedd74197f12fb8c30f259207430713291e8ec0.tar.bz2 | |
Merge up to ad87fbd1cf28760795c4e18f3318a2d720e5a8a6 from upstream
Conflicts:
* `doc/openocd.texi`: due to d382c95d57c0ad9ed2dcc83c95404babb7647708,
resolved by selecting the upstream version.
* `src/server/gdb_server.c`: between
944fe66f104e356c5fcd2b5c25200cebef9b389c and
92e8823ebdb6d01b41bb5d79af49501d525acd1d. Resolved by adopting the use
of `LOG_TARGET_*`.
* `src/target/target.c`: between
639e68a621b7ae8c4a296ca7e45b47075268fded and
c5358c84ad0d3e7497498e0457cec7785f72910a, selected the version from
`riscv-openocd`.
Change-Id: Ic1327f25e147945e0ec82947a82452501e8ee5de
Diffstat (limited to 'tcl/target/c100helper.tcl')
| -rw-r--r-- | tcl/target/c100helper.tcl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl index d1d3f25..ba0e4fe 100644 --- a/tcl/target/c100helper.tcl +++ b/tcl/target/c100helper.tcl @@ -176,7 +176,7 @@ proc setupAmbaClk {} { mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 # wait for PLL to lock echo "Waiting for Amba PLL to lock" - while {[expr {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK]} == 0} { sleep 1 } + while {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK == 0} { sleep 1 } # remove the internal PLL bypass mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL # remove PLL from BYPASS mode using MUX @@ -250,7 +250,7 @@ proc setupArmClk {} { mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 # wait for PLL to lock echo "Waiting for Amba PLL to lock" - while {[expr {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK]} == 0} { sleep 1 } + while {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK == 0} { sleep 1 } # remove the internal PLL bypass mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL # remove PLL from BYPASS mode using MUX |