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| author | Tim Newsome <tim@sifive.com> | 2020-08-18 11:07:34 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-18 11:07:34 -0700 |
| commit | c116dc50b221c2fecb54791e9f2f3f6aec38520c (patch) | |
| tree | e5aae542f69c14e4b743d822cc4ff4d421fadc7b /tcl/mmr_helpers.tcl | |
| parent | 53ec10b61da5de553c01f92bddf80c076bd49331 (diff) | |
| download | riscv-openocd-c116dc50b221c2fecb54791e9f2f3f6aec38520c.zip riscv-openocd-c116dc50b221c2fecb54791e9f2f3f6aec38520c.tar.gz riscv-openocd-c116dc50b221c2fecb54791e9f2f3f6aec38520c.tar.bz2 | |
Update to version 1.0 of the vector spec. (#505)
Accessing registers on targets that implement 0.9 or earlier will no
longer work. If you need that we can talk about making it a config
option.
Change-Id: I953b639cf9a92ee9b0422e035da57c1d07504237
Diffstat (limited to 'tcl/mmr_helpers.tcl')
0 files changed, 0 insertions, 0 deletions