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authorSergio Chico <sergio.chico@gmail.com>2013-11-10 16:03:40 +0100
committerAndreas Fritiofson <andreas.fritiofson@gmail.com>2013-12-14 21:53:16 +0000
commit93a3a82e49e7d1df855095dd541e9c04ad7823bc (patch)
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parent2d64cf92aed12fc785afe8bd8bd759ae28a6b2eb (diff)
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topic: Support for the Xilinx BSCAN_* Virtual JTAG in Openrisc
This add support to the Xilinx BSCAN_* virtual JTAG interface. This is the Xilinx equivalent of the Altera sld_virtual_jtag interface, it allows a user to connect to the debug unit through the main FPGA JTAG connection. Change-Id: Ia438e910650cff9cbc8f810b719fc1d5de5a8188 Signed-off-by: Sergio Chico <sergio.chico@gmail.com> Reviewed-on: http://openocd.zylin.com/1806 Tested-by: jenkins Reviewed-by: Franck Jullien <franck.jullien@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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