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| author | Jonathan McDowell <noodles@earth.li> | 2019-01-14 10:51:37 +0000 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2019-01-23 15:26:48 +0000 |
| commit | d2fb461621dc97a611e7bb44a2a64e1efe300875 (patch) | |
| tree | b2ebaabe29efe6ab9d95bbac81e580a25d6f4eed /tcl/board | |
| parent | 45b4998e9369029d48c1f33fbccb1a525793cd46 (diff) | |
| download | riscv-openocd-d2fb461621dc97a611e7bb44a2a64e1efe300875.zip riscv-openocd-d2fb461621dc97a611e7bb44a2a64e1efe300875.tar.gz riscv-openocd-d2fb461621dc97a611e7bb44a2a64e1efe300875.tar.bz2 | |
Correct ZynqMP configuration to be appropriately named
The xilinx_ultrascale.cfg target is actually the configuration for a
ZynqMP, which is a combination of an UltraScale+ FPGA core and a quad
core A53. Update the filename/comments to reflect this, and include
the tap IDs for all known FPGA cores for this part.
Change-Id: I70dfcc99861a482b83b6a795e83021d9cf1fe047
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-on: http://openocd.zylin.com/4850
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'tcl/board')
| -rw-r--r-- | tcl/board/avnet_ultrazed-eg.cfg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tcl/board/avnet_ultrazed-eg.cfg b/tcl/board/avnet_ultrazed-eg.cfg index a0ac5c6..9879bfc 100644 --- a/tcl/board/avnet_ultrazed-eg.cfg +++ b/tcl/board/avnet_ultrazed-eg.cfg @@ -1,6 +1,6 @@ # # AVNET UltraZED EG StarterKit -# UlraScale-EG plus IO Carrier with on-board digilent smt2 +# ZynqMP UlraScale-EG plus IO Carrier with on-board digilent smt2 # source [find interface/ftdi/digilent_jtag_smt2_nc.cfg] # jtag transport only @@ -13,4 +13,4 @@ adapter_khz 1000 set CHIPNAME uscale -source [find target/xilinx_ultrascale.cfg] +source [find target/xilinx_zynqmp.cfg] |