diff options
author | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-21 18:48:22 +0000 |
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committer | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-21 18:48:22 +0000 |
commit | 71af49ca7fb11b0bd0c1ba9578826f49288b68ef (patch) | |
tree | 9ba8dd705f83aa44879bc7b5817ce40317f1fc28 /tcl/board | |
parent | 86a7d813a165fda2816b8152342219b6c4ae2fc4 (diff) | |
download | riscv-openocd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.zip riscv-openocd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.tar.gz riscv-openocd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.tar.bz2 |
Remove annoying end-of-line whitespace from tcl/* files
git-svn-id: svn://svn.berlios.de/openocd/trunk@2743 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'tcl/board')
-rw-r--r-- | tcl/board/arm_evaluator7t.cfg | 2 | ||||
-rw-r--r-- | tcl/board/at91rm9200-dk.cfg | 10 | ||||
-rw-r--r-- | tcl/board/at91sam9g20-ek.cfg | 4 | ||||
-rw-r--r-- | tcl/board/atmel_at91sam9260-ek.cfg | 4 | ||||
-rw-r--r-- | tcl/board/crossbow_tech_imote2.cfg | 2 | ||||
-rw-r--r-- | tcl/board/csb732.cfg | 12 | ||||
-rw-r--r-- | tcl/board/digi_connectcore_wi-9c.cfg | 28 | ||||
-rw-r--r-- | tcl/board/eir.cfg | 24 | ||||
-rw-r--r-- | tcl/board/hitex_str9-comstick.cfg | 16 | ||||
-rw-r--r-- | tcl/board/imx27ads.cfg | 46 | ||||
-rw-r--r-- | tcl/board/imx27lnst.cfg | 24 | ||||
-rw-r--r-- | tcl/board/imx31pdk.cfg | 2 | ||||
-rw-r--r-- | tcl/board/mini2440.cfg | 134 | ||||
-rw-r--r-- | tcl/board/propox_mmnet1001.cfg | 2 | ||||
-rw-r--r-- | tcl/board/pxa255_sst.cfg | 2 | ||||
-rw-r--r-- | tcl/board/sheevaplug.cfg | 2 | ||||
-rw-r--r-- | tcl/board/str910-eval.cfg | 20 | ||||
-rw-r--r-- | tcl/board/telo.cfg | 8 | ||||
-rw-r--r-- | tcl/board/unknown_at91sam9260.cfg | 10 | ||||
-rw-r--r-- | tcl/board/x300t.cfg | 6 | ||||
-rw-r--r-- | tcl/board/zy1000.cfg | 30 |
21 files changed, 194 insertions, 194 deletions
diff --git a/tcl/board/arm_evaluator7t.cfg b/tcl/board/arm_evaluator7t.cfg index 9cca239..52de57a 100644 --- a/tcl/board/arm_evaluator7t.cfg +++ b/tcl/board/arm_evaluator7t.cfg @@ -2,7 +2,7 @@ source [find target/samsung_s3c4510.cfg] -# +# # FIXME: # Add (A) sdram configuration # Add (B) flash cfi programing configuration diff --git a/tcl/board/at91rm9200-dk.cfg b/tcl/board/at91rm9200-dk.cfg index 900ee35..9a6f89e 100644 --- a/tcl/board/at91rm9200-dk.cfg +++ b/tcl/board/at91rm9200-dk.cfg @@ -16,7 +16,7 @@ proc at91rm9200_dk_init { } { # Try to run at 1khz... Yea, that slow! # Chip is really running @ 32khz jtag_khz 8 - + mww 0xfffffc64 0xffffffff ## disable all clocks but system clock mww 0xfffffc04 0xfffffffe @@ -37,14 +37,14 @@ proc at91rm9200_dk_init { } { mww 0xfffffc30 0x202 ## Sleep some - (go read) sleep 100 - + #======================================== # CPU now runs at 180mhz # SYS runs at 60mhz. jtag_khz 40000 #======================================== - - + + ## set memc for all memories mww 0xffffff60 0x02 ## program smc controller @@ -55,7 +55,7 @@ proc at91rm9200_dk_init { } { mww 0xffffff80 0x02 ## touch sdram chip to make it work mww 0x20000000 0 - ## sdram controller mode register + ## sdram controller mode register mww 0xffffff90 0x04 mww 0x20000000 0 mww 0x20000000 0 diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg index c9deb14..00ab7fa 100644 --- a/tcl/board/at91sam9g20-ek.cfg +++ b/tcl/board/at91sam9g20-ek.cfg @@ -62,7 +62,7 @@ proc read_register {register} { } proc at91sam9g20_init { } { - + # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires # a number of steps that must be carefully performed. The process outline below follows the # recommended procedure outlined in the AT91SAM9G20 technical manual. @@ -94,7 +94,7 @@ proc at91sam9g20_init { } { mww 0xfffffc30 0x00000101 while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } - + # Now change PMC_MCKR register to select PLLA. # Wait for MCKRDY signal from PMC_SR to assert. diff --git a/tcl/board/atmel_at91sam9260-ek.cfg b/tcl/board/atmel_at91sam9260-ek.cfg index 0d9d002..099d93d 100644 --- a/tcl/board/atmel_at91sam9260-ek.cfg +++ b/tcl/board/atmel_at91sam9260-ek.cfg @@ -26,7 +26,7 @@ $_TARGETNAME configure -event reset-start { # RSTC_MR : enable user reset, MMU may be enabled... use physical address arm926ejs mww_phys 0xfffffd08 0xa5000501 } - + $_TARGETNAME configure -event reset-init { mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog @@ -48,7 +48,7 @@ $_TARGETNAME configure -event reset-init { mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31 mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31 - + mww 0xffffef1c 0x00010002 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks) diff --git a/tcl/board/crossbow_tech_imote2.cfg b/tcl/board/crossbow_tech_imote2.cfg index 7e9d487..a7d1215 100644 --- a/tcl/board/crossbow_tech_imote2.cfg +++ b/tcl/board/crossbow_tech_imote2.cfg @@ -4,7 +4,7 @@ set CHIPNAME imote2 source [find target/pxa270.cfg] # longer-than-normal reset delay -jtag_nsrst_delay 800 +jtag_nsrst_delay 800 reset_config trst_and_srst separate diff --git a/tcl/board/csb732.cfg b/tcl/board/csb732.cfg index 8bf77cb..1787323 100644 --- a/tcl/board/csb732.cfg +++ b/tcl/board/csb732.cfg @@ -11,7 +11,7 @@ $_TARGETNAME configure -event reset-init { csb732_init } # Bare-bones initialization of core clocks and SDRAM proc csb732_init { } { - + # Disable fast writing only for init memwrite burst disable @@ -29,17 +29,17 @@ proc csb732_init { } { # Set ARM clock to 532 MHz, AHB to 133 MHz mww 0x53F80004 0x1000 - + # Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz mww 0x53F8001C 0xB2C01 - + set ESDMISC 0xB8001010 set ESDCFG0 0xB8001004 set ESDCTL0 0xB8001000 # Enable DDR mww $ESDMISC 0x4 - + # Timing mww $ESDCFG0 0x007fff3f @@ -51,7 +51,7 @@ proc csb732_init { } { # Enable CS) auto-refresh mww $ESDCTL0 0xA2120080 - + # Refresh twice (dummy writes) mww 0x80000000 0 mww 0x80000000 0 @@ -59,7 +59,7 @@ proc csb732_init { } { # Enable CS0 load mode register mww $ESDCTL0 0xB2120080 - # Dummy writes + # Dummy writes mwb 0x80000033 0x01 mwb 0x81000000 0x01 diff --git a/tcl/board/digi_connectcore_wi-9c.cfg b/tcl/board/digi_connectcore_wi-9c.cfg index f8b8912..58f12a6 100644 --- a/tcl/board/digi_connectcore_wi-9c.cfg +++ b/tcl/board/digi_connectcore_wi-9c.cfg @@ -4,15 +4,15 @@ reset_config trst_and_srst -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME ns9360 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { # This config file was defaulting to big endian.. set _ENDIAN big } @@ -46,17 +46,17 @@ $_TARGETNAME configure -event reset-init { mww 0x90600104 0x33313333 mww 0xA0700000 0x00000001 # Enable the memory controller. mww 0xA0700024 0x00000006 # Set the refresh counter 6 - mww 0xA0700028 0x00000001 # + mww 0xA0700028 0x00000001 # mww 0xA0700030 0x00000001 # Set the precharge period mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles mww 0xA070003C 0x00000001 # tAPR mww 0xA0700040 0x00000005 # tDAL mww 0xA0700044 0x00000001 # tWR - mww 0xA0700048 0x00000006 # tRC 32 clock cycles + mww 0xA0700048 0x00000006 # tRC 32 clock cycles mww 0xA070004C 0x00000006 # tRFC 32 clock cycles mww 0xA0700054 0x00000001 # tRRD mww 0xA0700058 0x00000001 # tMRD - mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4) + mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4) mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5) mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6) mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7) @@ -79,11 +79,11 @@ $_TARGETNAME configure -event reset-init { mww 0xA0900000 0x00000002 mww 0xA0900000 0x00000002 # - mdw 0xA0900000 - mdw 0xA0900000 - mdw 0xA0900000 - mdw 0xA0900000 - mdw 0xA0900000 + mdw 0xA0900000 + mdw 0xA0900000 + mdw 0xA0900000 + mdw 0xA0900000 + mdw 0xA0900000 # mww 0xA0700024 0x00000030 # Set the refresh counter to 30 mww 0xA0700020 0x00000083 # Issue SDRAM MODE command diff --git a/tcl/board/eir.cfg b/tcl/board/eir.cfg index 0876565..3754a42 100644 --- a/tcl/board/eir.cfg +++ b/tcl/board/eir.cfg @@ -4,7 +4,7 @@ source [find target/sam7se512.cfg] $_TARGETNAME configure -event reset-init { - # WDT_MR, disable watchdog + # WDT_MR, disable watchdog mww 0xFFFFFD44 0x00008000 # RSTC_MR, enable user reset @@ -51,31 +51,31 @@ $_TARGETNAME configure -event reset-init { # Issue 16 bit SDRAM command: NOP mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 + mww 0x20000000 0x00000000 # Issue 16 bit SDRAM command: Precharge all mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 + mww 0x20000000 0x00000000 # Issue 8 auto-refresh cycles mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 + mww 0x20000000 0x00000000 mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 + mww 0x20000000 0x00000000 mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 + mww 0x20000000 0x00000000 mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 + mww 0x20000000 0x00000000 mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 + mww 0x20000000 0x00000000 mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 + mww 0x20000000 0x00000000 mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 + mww 0x20000000 0x00000000 mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 + mww 0x20000000 0x00000000 - # Issue 16 bit SDRAM command: Set mode register + # Issue 16 bit SDRAM command: Set mode register mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF mww 0x20000014 0xcafedede diff --git a/tcl/board/hitex_str9-comstick.cfg b/tcl/board/hitex_str9-comstick.cfg index de4d56d..25ff784 100644 --- a/tcl/board/hitex_str9-comstick.cfg +++ b/tcl/board/hitex_str9-comstick.cfg @@ -14,15 +14,15 @@ reset_config trst_and_srst #jtag scan chain #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME str912 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } @@ -56,10 +56,10 @@ target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME $_TARGETNAME configure -event reset-init { # We can increase speed now that we know the target is halted. #jtag_rclk 3000 - + # -- Enable 96K RAM # PFQBC enabled / DTCM & AHB wait-states disabled - mww 0x5C002034 0x0191 + mww 0x5C002034 0x0191 str9x flash_config 0 4 2 0 0x80000 flash protect 0 0 7 off diff --git a/tcl/board/imx27ads.cfg b/tcl/board/imx27ads.cfg index dc0de4a..664b470 100644 --- a/tcl/board/imx27ads.cfg +++ b/tcl/board/imx27ads.cfg @@ -24,52 +24,52 @@ proc imx27ads_init { } { # ======================================== # Configure DDR on CSD0 -- initial reset # ======================================== - mww 0xD8001010 0x00000008 + mww 0xD8001010 0x00000008 # ======================================== - # Configure PSRAM on CS5 + # Configure PSRAM on CS5 # ======================================== mww 0xd8002050 0x0000dcf6 - mww 0xd8002054 0x444a4541 - mww 0xd8002058 0x44443302 + mww 0xd8002054 0x444a4541 + mww 0xd8002058 0x44443302 # ======================================== # Configure16 bit NorFlash on CS0 # ======================================== - mww 0xd8002000 0x0000CC03 - mww 0xd8002004 0xa0330D01 - mww 0xd8002008 0x00220800 + mww 0xd8002000 0x0000CC03 + mww 0xd8002004 0xa0330D01 + mww 0xd8002008 0x00220800 # ======================================== - # Configure CPLD on CS4 + # Configure CPLD on CS4 # ======================================== - mww 0xd8002040 0x0000DCF6 - mww 0xd8002044 0x444A4541 - mww 0xd8002048 0x44443302 + mww 0xd8002040 0x0000DCF6 + mww 0xd8002044 0x444A4541 + mww 0xd8002048 0x44443302 # ======================================== - # Configure DDR on CSD0 -- wait 5000 cycle + # Configure DDR on CSD0 -- wait 5000 cycle # ======================================== - mww 0x10027828 0x55555555 - mww 0x10027830 0x55555555 - mww 0x10027834 0x55555555 - mww 0x10027838 0x00005005 - mww 0x1002783C 0x15555555 + mww 0x10027828 0x55555555 + mww 0x10027830 0x55555555 + mww 0x10027834 0x55555555 + mww 0x10027838 0x00005005 + mww 0x1002783C 0x15555555 - mww 0xD8001010 0x00000004 + mww 0xD8001010 0x00000004 - mww 0xD8001004 0x00795729 + mww 0xD8001004 0x00795729 - mww 0xD8001000 0x92200000 + mww 0xD8001000 0x92200000 mww 0xA0000F00 0x0 - mww 0xD8001000 0xA2200000 + mww 0xD8001000 0xA2200000 mww 0xA0000F00 0x0 mww 0xA0000F00 0x0 - mww 0xD8001000 0xB2200000 + mww 0xD8001000 0xB2200000 mwb 0xA0000033 0xFF mwb 0xA1000000 0xAA - mww 0xD8001000 0x82228085 + mww 0xD8001000 0x82228085 } diff --git a/tcl/board/imx27lnst.cfg b/tcl/board/imx27lnst.cfg index 2ee7f09..ae141d4 100644 --- a/tcl/board/imx27lnst.cfg +++ b/tcl/board/imx27lnst.cfg @@ -22,38 +22,38 @@ proc imx27lnst_init { } { # ======================================== # Configure DDR on CSD0 -- initial reset # ======================================== - mww 0xD8001010 0x00000008 + mww 0xD8001010 0x00000008 sleep 100 # ======================================== - # Configure DDR on CSD0 -- wait 5000 cycle + # Configure DDR on CSD0 -- wait 5000 cycle # ======================================== - mww 0x10027828 0x55555555 - mww 0x10027830 0x55555555 - mww 0x10027834 0x55555555 - mww 0x10027838 0x00005005 - mww 0x1002783C 0x15555555 + mww 0x10027828 0x55555555 + mww 0x10027830 0x55555555 + mww 0x10027834 0x55555555 + mww 0x10027838 0x00005005 + mww 0x1002783C 0x15555555 - mww 0xD8001010 0x00000004 + mww 0xD8001010 0x00000004 - mww 0xD8001004 0x00795729 + mww 0xD8001004 0x00795729 #mww 0xD8001000 0x92200000 mww 0xD8001000 0x91120000 mww 0xA0000F00 0x0 - #mww 0xD8001000 0xA2200000 + #mww 0xD8001000 0xA2200000 mww 0xD8001000 0xA1120000 mww 0xA0000F00 0x0 mww 0xA0000F00 0x0 - #mww 0xD8001000 0xB2200000 + #mww 0xD8001000 0xB2200000 mww 0xD8001000 0xB1120000 mwb 0xA0000033 0xFF mwb 0xA1000000 0xAA - #mww 0xD8001000 0x82228085 + #mww 0xD8001000 0x82228085 mww 0xD8001000 0x81128080 } diff --git a/tcl/board/imx31pdk.cfg b/tcl/board/imx31pdk.cfg index 6723356..2318e44 100644 --- a/tcl/board/imx31pdk.cfg +++ b/tcl/board/imx31pdk.cfg @@ -25,7 +25,7 @@ proc imx31pdk_init { } { mww 0x53F80010 0x00271C1B # ======================================== - # Configure CPLD on CS5 + # Configure CPLD on CS5 # ======================================== mww 0xb8002050 0x0000DCF6 mww 0xb8002054 0x444A4541 diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg index 0b1d881..8497bdd 100644 --- a/tcl/board/mini2440.cfg +++ b/tcl/board/mini2440.cfg @@ -1,7 +1,7 @@ #------------------------------------------------------------------------- # Mini2440 Samsung s3c2440A Processor with 64MB DRAM, 64MB NAND, 2 MB N0R # NOTE: Configured for NAND boot (switch S2 in NANDBOOT) -# 64 MB NAND (Samsung K9D1208V0M) +# 64 MB NAND (Samsung K9D1208V0M) # B Findlay 08/09 # # ----------- Important notes to help you on your way ---------- @@ -9,9 +9,9 @@ # NOR/NAND Boot Switch - I have not read the vivi source, but from # what I could tell from reading the registers it appears that vivi # loads itself into DRAM and then flips NFCONT (0x4E000004) bits -# Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND -# FLASH at the bottom 64MB of memory. This essentially takes the -# NOR Flash out of the circuit so you can't trash it. +# Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND +# FLASH at the bottom 64MB of memory. This essentially takes the +# NOR Flash out of the circuit so you can't trash it. # # I adapted the samsung_s3c2440.cfg file which is why I did not # include "source [find target/samsung_s3c2440.cfg]". I believe @@ -22,9 +22,9 @@ # JTAG ADAPTER SPECIFIC # IMPORTANT! Any JTAG device that uses ADAPTIVE CLOCKING will likely # FAIL as the pin RTCK on the mini2440 10 pin JTAG Conn doesn't exist. -# This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is +# This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is # necessary to FORCE setting the clock. Normally this should be configured -# in the openocd.cfg file, but was placed here as it can be a tough +# in the openocd.cfg file, but was placed here as it can be a tough # problem to figure out. THIS MAY NOT FIX YOUR PROBLEM.. I modified # the openOCD driver jlink.c and posted it here. It may eventually end # up changed in openOCD, but its a hack in the driver and really should @@ -42,21 +42,21 @@ # But it should get you way ahead of the game from where I started. # If you find problems (and fixes) please post them to # openocd-development@lists.berlios.de and join the developers and -# check in fixes to this and anything else you find. I do not -# provide support, but if you ask really nice and I see anything +# check in fixes to this and anything else you find. I do not +# provide support, but if you ask really nice and I see anything # obvious I will tell you.. mostly just dig, fix, and submit to openocd. -# +# # best! brfindla@yahoo.com Nashua, NH USA # # Recommended resources: # - first two are the best Mini2440 resources anywhere # - maintained by buserror... thanks guy! # -# http://bliterness.blogspot.com/ +# http://bliterness.blogspot.com/ # http://code.google.com/p/mini2440/ # # others.... -# +# # http://forum.sparkfun.com/viewforum.php?f=18 # http://labs.kernelconcepts.de/Publications/Micro24401/ # http://www.friendlyarm.net/home @@ -75,19 +75,19 @@ # Target configuration for the Samsung 2440 system on chip # Tested on a S3C2440 Evaluation board by keesj # Processor : ARM920Tid(wb) rev 0 (v4l) -# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d +# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d # (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0) #------------------------------------------------------------------------- -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME s3c2440 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { # this defaults to a bigendian set _ENDIAN little } @@ -108,16 +108,16 @@ $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area- #reset configuration jtag_nsrst_delay 100 -jtag_ntrst_delay 100 +jtag_ntrst_delay 100 reset_config trst_and_srst #------------------------------------------------------------------------- # JTAG ADAPTER SPECIFIC -# IMPORTANT! See README at top of this file. +# IMPORTANT! See README at top of this file. #------------------------------------------------------------------------- - jtag_khz 12000 - jtag interface + jtag_khz 12000 + jtag interface #------------------------------------------------------------------------- # GDB Setup @@ -125,23 +125,23 @@ reset_config trst_and_srst gdb_port 3333 gdb_detach resume - gdb_breakpoint_override hard + gdb_breakpoint_override hard gdb_memory_map enable - gdb_flash_program enable + gdb_flash_program enable #------------------------------------------------ # ARM SPECIFIC #------------------------------------------------ - targets + targets # arm7_9 dcc_downloads enable # arm7_9 fast_memory_access enable - - - nand device s3c2440 0 + + + nand device s3c2440 0 jtag_nsrst_delay 100 - jtag_ntrst_delay 100 + jtag_ntrst_delay 100 reset_config trst_and_srst init @@ -180,59 +180,59 @@ proc init_2440 { } { # OM2 OM3 pulled to ground so main clock and # usb clock are off 12mHz xtal #----------------------------------------------- - + arm920t mww_phys 0x4C000014 0x00000005 # Clock Divider control Reg arm920t mww_phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register arm920t mww_phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg arm920t mww_phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg - + #----------------------------------------------- # Configure Memory controller # BWSCON configures all banks, NAND, NOR, DRAM # DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7 #----------------------------------------------- - + arm920t mww_phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width arm920t mww_phys 0x48000010 0x00001112 # BANKCON4 - ? - arm920t mww_phys 0x4800001c 0x00018009 # BANKCON6 - DRAM - arm920t mww_phys 0x48000020 0x00018009 # BANKCON7 - DRAM - arm920t mww_phys 0x48000024 0x008E04EB # REFRESH - DRAM - arm920t mww_phys 0x48000028 0x000000B2 # BANKSIZE - DRAM - arm920t mww_phys 0x4800002C 0x00000030 # MRSRB6 - DRAM - arm920t mww_phys 0x48000030 0x00000030 # MRSRB7 - DRAM - + arm920t mww_phys 0x4800001c 0x00018009 # BANKCON6 - DRAM + arm920t mww_phys 0x48000020 0x00018009 # BANKCON7 - DRAM + arm920t mww_phys 0x48000024 0x008E04EB # REFRESH - DRAM + arm920t mww_phys 0x48000028 0x000000B2 # BANKSIZE - DRAM + arm920t mww_phys 0x4800002C 0x00000030 # MRSRB6 - DRAM + arm920t mww_phys 0x48000030 0x00000030 # MRSRB7 - DRAM + #----------------------------------------------- # Now port configuration for enables for memory # and other stuff. #----------------------------------------------- - + arm920t mww_phys 0x56000000 0x007FFFFF # GPACON - - arm920t mww_phys 0x56000010 0x00295559 # GPBCON + + arm920t mww_phys 0x56000010 0x00295559 # GPBCON arm920t mww_phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE) - arm920t mww_phys 0x56000014 0x000007C2 # GPBDAT - - arm920t mww_phys 0x56000020 0xAAAAA6AA # GPCCON + arm920t mww_phys 0x56000014 0x000007C2 # GPBDAT + + arm920t mww_phys 0x56000020 0xAAAAA6AA # GPCCON arm920t mww_phys 0x56000028 0x0000FFFF # GPCUP - arm920t mww_phys 0x56000024 0x00000020 # GPCDAT - - arm920t mww_phys 0x56000030 0xAAAAAAAA # GPDCON - arm920t mww_phys 0x56000038 0x0000FFFF # GPDUP - - arm920t mww_phys 0x56000040 0xAAAAAAAA # GPECON - arm920t mww_phys 0x56000048 0x0000FFFF # GPEUP - - arm920t mww_phys 0x56000050 0x00001555 # GPFCON - arm920t mww_phys 0x56000058 0x0000007F # GPFUP - arm920t mww_phys 0x56000054 0x00000000 # GPFDAT - - arm920t mww_phys 0x56000060 0x00150114 # GPGCON - arm920t mww_phys 0x56000068 0x0000007F # GPGUP - - arm920t mww_phys 0x56000070 0x0015AAAA # GPHCON - arm920t mww_phys 0x56000078 0x000003FF # GPGUP - -} + arm920t mww_phys 0x56000024 0x00000020 # GPCDAT + + arm920t mww_phys 0x56000030 0xAAAAAAAA # GPDCON + arm920t mww_phys 0x56000038 0x0000FFFF # GPDUP + + arm920t mww_phys 0x56000040 0xAAAAAAAA # GPECON + arm920t mww_phys 0x56000048 0x0000FFFF # GPEUP + + arm920t mww_phys 0x56000050 0x00001555 # GPFCON + arm920t mww_phys 0x56000058 0x0000007F # GPFUP + arm920t mww_phys 0x56000054 0x00000000 # GPFDAT + + arm920t mww_phys 0x56000060 0x00150114 # GPGCON + arm920t mww_phys 0x56000068 0x0000007F # GPGUP + + arm920t mww_phys 0x56000070 0x0015AAAA # GPHCON + arm920t mww_phys 0x56000078 0x000003FF # GPGUP + +} @@ -243,7 +243,7 @@ proc flash_config { } { #----------------------------------------- halt - + #flash configuration (K9D1208V0M: 512Mbit, x8, 3.3V, Mode: Normal, 1st gen) nand probe 0 nand list @@ -275,8 +275,8 @@ proc load_uboot { } { echo "---- http://repo.or.cz/w/u-boot-openmoko/mini2440.git ---" echo "---- Also this: ---" echo "---- http://code.google.com/p/mini2440/wiki/MiniBringup --" - echo "----------------------------------------------------------" - + echo "----------------------------------------------------------" + init_2440 echo "Loading /tftpboot/u-boot-nand512.bin" load_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin diff --git a/tcl/board/propox_mmnet1001.cfg b/tcl/board/propox_mmnet1001.cfg index aa6681e..8972633 100644 --- a/tcl/board/propox_mmnet1001.cfg +++ b/tcl/board/propox_mmnet1001.cfg @@ -9,7 +9,7 @@ $_TARGETNAME configure -event reset-init {at91sam_init} proc at91sam_init { } { - + # at reset chip runs at 32 kHz => 1/8 * 32 kHz = 4 kHz jtag_rclk 4 diff --git a/tcl/board/pxa255_sst.cfg b/tcl/board/pxa255_sst.cfg index 76ae4c9..d9f6187 100644 --- a/tcl/board/pxa255_sst.cfg +++ b/tcl/board/pxa255_sst.cfg @@ -1,7 +1,7 @@ # A PXA255 test board with SST 39LF400A flash # # At reset the memory map is as follows. Note that -# the memory map changes later on as the application +# the memory map changes later on as the application # starts... # # RAM at 0x4000000 diff --git a/tcl/board/sheevaplug.cfg b/tcl/board/sheevaplug.cfg index 6fe3ce3..1a3f61b 100644 --- a/tcl/board/sheevaplug.cfg +++ b/tcl/board/sheevaplug.cfg @@ -1,4 +1,4 @@ -# Marvell SheevaPlug +# Marvell SheevaPlug source [find interface/sheevaplug.cfg] source [find target/feroceon.cfg] diff --git a/tcl/board/str910-eval.cfg b/tcl/board/str910-eval.cfg index 10a2100..e98c1c7 100644 --- a/tcl/board/str910-eval.cfg +++ b/tcl/board/str910-eval.cfg @@ -1,17 +1,17 @@ # str910-eval eval board -# -# Need reset scripts +# +# Need reset scripts reset_config trst_and_srst -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME str912 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } @@ -44,10 +44,10 @@ $_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000 -wo $_TARGETNAME configure -event reset-init { # We can increase speed now that we know the target is halted. #jtag_rclk 3000 - + # -- Enable 96K RAM # PFQBC enabled / DTCM & AHB wait-states disabled - mww 0x5C002034 0x0191 + mww 0x5C002034 0x0191 str9x flash_config 0 4 2 0 0x80000 flash protect 0 0 7 off diff --git a/tcl/board/telo.cfg b/tcl/board/telo.cfg index d740db2..a0643f7 100644 --- a/tcl/board/telo.cfg +++ b/tcl/board/telo.cfg @@ -8,7 +8,7 @@ source [find target/c100helper.tcl] # Telo board & C100 support trst and srst -# however openocd does not support +# however openocd does not support # 1. setting srst reset pulse width # 2. setting delay between srst pulse and JTAG access # This really makes the srst useless for now. @@ -23,7 +23,7 @@ $_TARGETNAME configure -event reset-init { # setup GPIO used as control signals for C100 setupGPIO # This will allow acces to lower 8MB or NOR - lowGPIO5 + lowGPIO5 # setup NOR size,timing,etc. setupNOR # setup internals + PLL + DDR2 @@ -38,10 +38,10 @@ $_TARGETNAME configure -event reset-deassert-post { # Force target into ARM state. # soft_reset_halt # not implemented on ARM11 puts "Detected SRSRT asserted on C100.CPU" - + } -proc power_restore {} { puts "Sensed power restore. No action." } +proc power_restore {} { puts "Sensed power restore. No action." } proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." } diff --git a/tcl/board/unknown_at91sam9260.cfg b/tcl/board/unknown_at91sam9260.cfg index 3337eea..017f793 100644 --- a/tcl/board/unknown_at91sam9260.cfg +++ b/tcl/board/unknown_at91sam9260.cfg @@ -1,4 +1,4 @@ -# Thanks to Pieter Conradie for this script! +# Thanks to Pieter Conradie for this script! # # Unknown vendor board contains: # @@ -15,12 +15,12 @@ source [find target/at91sam9260.cfg] $_TARGETNAME configure -event reset-start { # At reset CPU runs at 22 to 42 kHz. # JTAG Frequency must be 6 times slower. - jtag_rclk 3 + jtag_rclk 3 halt # RSTC_MR : enable user reset, MMU may be enabled... use physical address arm926ejs mww_phys 0xfffffd08 0xa5000501 } - + $_TARGETNAME configure -event reset-init { mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog @@ -37,7 +37,7 @@ $_TARGETNAME configure -event reset-init { sleep 10 # wait 10 ms # Increase JTAG Speed to 6 MHz if RCLK is not supported - jtag_rclk 6000 + jtag_rclk 6000 arm7_9 dcc_downloads enable # Enable faster DCC downloads @@ -51,7 +51,7 @@ $_TARGETNAME configure -event reset-init { mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31 mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31 mww 0xfffff860 0xffff0000 # PIO_PUDR : Disable D15..D31 pull-ups - + mww 0xffffef1c 0x00010102 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM # VDDIOMSEL set for +3V3 memory # Disable D0..D15 pull-ups diff --git a/tcl/board/x300t.cfg b/tcl/board/x300t.cfg index 985f44e..3b09493 100644 --- a/tcl/board/x300t.cfg +++ b/tcl/board/x300t.cfg @@ -18,13 +18,13 @@ proc x300t_init { } { mww 0xa0030000 0xE34111BA mww 0xa003fffc 0xa4444 mww 0xa003fffc 0 - + # remap boot vector in CPU local RAM mww 0xa006f000 0x60000 - + # map flash to CPU address space REG_BASE_cpu_block+CPU_remap4 mww 0x0006f010 0x48000000 - + # map flash addr to REG_BASE_cpu_block + LR_XENV_LOCATION (normally done by XOS) mww 0x00061ff0 0x48000000 } diff --git a/tcl/board/zy1000.cfg b/tcl/board/zy1000.cfg index d8bb465..07f5ee9 100644 --- a/tcl/board/zy1000.cfg +++ b/tcl/board/zy1000.cfg @@ -10,19 +10,19 @@ reset_config srst_only srst_pulls_trst -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { set _CHIPNAME zy1000 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } - + #jtag scan chain if { [info exists CPUTAPID ] } { set _CPUTAPID $CPUTAPID @@ -39,7 +39,7 @@ arm7_9 fast_memory_access enable arm7_9 dcc_downloads enable flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf -$_TARGETNAME configure -event reset-init { +$_TARGETNAME configure -event reset-init { # Set up chip selects & timings mww 0xFFE00000 0x0100273D mww 0xFFE00004 0x08002125 @@ -51,12 +51,12 @@ $_TARGETNAME configure -event reset-init { mww 0xFFE0001c 0x70000000 mww 0xFFE00020 0x00000001 mww 0xFFE00024 0x00000000 - - # remap - mww 0xFFFFF124 0xFFFFFFFF + + # remap + mww 0xFFFFF124 0xFFFFFFFF mww 0xffff0010 0x100 mww 0xffff0034 0x100 - + #disable 16x5x UART interrupts mww 0x08020004 0 } @@ -75,7 +75,7 @@ proc production_info {} { # There is no return value from this procedure. If it is # successful it does not throw an exception # -# Progress messages are output via puts +# Progress messages are output via puts proc production {firmwarefile serialnumber} { if {[string length $serialnumber]!=12} { puts "Invalid serial number" @@ -92,11 +92,11 @@ proc production {firmwarefile serialnumber} { verify_image $firmwarefile 0x1000000 bin # Big endian... weee!!!! - puts "Setting MAC number to $serialnumber" + puts "Setting MAC number to $serialnumber" flash fillw [expr 0x1030000-0x8] "0x[string range $serialnumber 2 3][string range $serialnumber 0 1]0000" 1 flash fillw [expr 0x1030000-0x4] "0x[string range $serialnumber 10 11][string range $serialnumber 8 9][string range $serialnumber 6 7][string range $serialnumber 4 5]" 1 puts "Production successful" -} +} proc production_test {} { |