Merge remote-tracking branch 'origin/riscv' into riscv-compliance-rebase

22 files changed, 189 insertions, 38 deletions

diff --git a/tcl/board/8devices-lima.cfg b/tcl/board/8devices-lima.cfg
new file mode 100644
index 0000000..136f861
--- /dev/null
+++ b/tcl/board/8devices-lima.cfg
@@ -0,0 +1,30 @@
+# Product page:
+# https://www.8devices.com/products/lima
+#
+# Location of JTAG pins:
+# J2 GPIO0	JTAG TCK
+# J2 GPIO1	JTAG TDI
+# J2 GPIO2	JTAG TDO
+# J2 GPIO3	JTAG TMS
+# J2 RST	directly connected to RESET_L of the SoC and can be used as
+#               JTAG SRST. Note: this pin will also reset the debug engine.
+# J1 +3,3V	Can be use as JTAG Vref
+# J1 or J2 GND	Can be used for JTAG GND
+#
+# This board is powered from mini USB connecter which is also used
+# as USB to UART converted based on FTDI FT230XQ chip
+
+source [find target/qualcomm_qca4531.cfg]
+
+proc board_init { } {
+	qca4531_ddr2_550_550_init
+}
+
+$_TARGETNAME configure -event reset-init {
+	board_init
+}
+
+set ram_boot_address 0xa0000000
+$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0
diff --git a/tcl/board/atmel_samd10_xplained_mini.cfg b/tcl/board/atmel_samd10_xplained_mini.cfg
new file mode 100644
index 0000000..64ae11e
--- /dev/null
+++ b/tcl/board/atmel_samd10_xplained_mini.cfg
@@ -0,0 +1,10 @@
+#
+# Atmel SAMD10 Xplained mini evaluation kit.
+# http://www.atmel.com/tools/atsamd10-xmini.aspx
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samd10d14
+
+source [find target/at91samdXX.cfg]
diff --git a/tcl/board/atmel_samd11_xplained_pro.cfg b/tcl/board/atmel_samd11_xplained_pro.cfg
new file mode 100644
index 0000000..8ce9751
--- /dev/null
+++ b/tcl/board/atmel_samd11_xplained_pro.cfg
@@ -0,0 +1,10 @@
+#
+# Atmel SAMD11 Xplained Pro evaluation kit.
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samd11d14
+
+source [find target/at91samdXX.cfg]
diff --git a/tcl/board/dptechnics_dpt-board-v1.cfg b/tcl/board/dptechnics_dpt-board-v1.cfg
new file mode 100644
index 0000000..de31c7c
--- /dev/null
+++ b/tcl/board/dptechnics_dpt-board-v1.cfg
@@ -0,0 +1,32 @@
+# Product page:
+# https://www.dptechnics.com/en/products/dpt-board-v1.html
+#
+# JTAG is a 5 pin array located close to main module in following order:
+# 1. JTAG TCK
+# 2. JTAG TDO
+# 3. JTAG TDI
+# 4. JTAG TMS
+# 5. GND	The GND is located near letter G of word JTAG on board.
+#
+# Two RST pins are connected to:
+# 1. GND
+# 2. GPIO11	this pin is located near letter R of word RST.
+#
+# To enable EJTAG mode, GPIO11 (RST[1]) pin should be pulled up. For example
+# with 10K resistor connected to V3.3 pin.
+#
+# This board is powered from micro USB connector. No real reset pin or button, for
+# example RESET_L is available.
+
+source [find target/atheros_ar9331.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	ar9331_25mhz_pll_init
+	sleep 1
+	ar9331_ddr2_init
+}
+
+set ram_boot_address 0xa0000000
+$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0
diff --git a/tcl/board/nxp_frdm-ls1012a.cfg b/tcl/board/nxp_frdm-ls1012a.cfg
new file mode 100644
index 0000000..3973b3c
--- /dev/null
+++ b/tcl/board/nxp_frdm-ls1012a.cfg
@@ -0,0 +1,15 @@
+#
+# NXP FRDM-LS1012A (Freedom)
+#
+
+#
+# NXP Kinetis K20
+#
+source [find interface/cmsis-dap.cfg]
+transport select jtag
+
+# Also offers a 10-pin 0.05" CoreSight JTAG connector.
+
+source [find target/ls1012a.cfg]
+
+reset_config srst_only
diff --git a/tcl/board/reflexces_achilles_i-dev_kit_arria10.cfg b/tcl/board/reflexces_achilles_i-dev_kit_arria10.cfg
new file mode 100644
index 0000000..a6e8065
--- /dev/null
+++ b/tcl/board/reflexces_achilles_i-dev_kit_arria10.cfg
@@ -0,0 +1,13 @@
+# Achilles Instant-Development Kit Arria 10 SoC SoM
+# https://www.reflexces.com/products-solutions/achilles-instant-development-kit-arria-10-soc-som
+#
+
+if { [info exists USE_EXTERNAL_DEBUGGER] } {
+	echo "Using external debugger"
+} else {
+	source [find interface/altera-usb-blaster2.cfg]
+	usb_blaster_device_desc "Arria10 IDK"
+}
+
+source [find fpga/altera-10m50.cfg]
+source [find target/altera_fpgasoc_arria10.cfg]
diff --git a/tcl/board/renesas_gen2_common.cfg b/tcl/board/renesas_gen2_common.cfg
new file mode 100644
index 0000000..00fa777
--- /dev/null
+++ b/tcl/board/renesas_gen2_common.cfg
@@ -0,0 +1,14 @@
+# Renesas R-Car Gen2 Evaluation Board common settings
+
+reset_config trst_and_srst srst_nogate
+
+proc init_reset {mode} {
+    # Assert both resets: equivalent to a power-on reset
+    jtag_reset 1 1
+
+    # Deassert TRST to begin TAP communication
+    jtag_reset 0 1
+
+    # TAP should now be responsive, validate the scan-chain
+    jtag arp_init
+}
diff --git a/tcl/board/renesas_porter.cfg b/tcl/board/renesas_porter.cfg
new file mode 100644
index 0000000..c8032f5
--- /dev/null
+++ b/tcl/board/renesas_porter.cfg
@@ -0,0 +1,4 @@
+# Renesas R-Car M2 Evaluation Board
+
+source [find target/renesas_r8a7791.cfg]
+source [find board/renesas_gen2_common.cfg]
diff --git a/tcl/board/renesas_silk.cfg b/tcl/board/renesas_silk.cfg
new file mode 100644
index 0000000..a026537
--- /dev/null
+++ b/tcl/board/renesas_silk.cfg
@@ -0,0 +1,4 @@
+# Renesas R-Car E2 Evaluation Board
+
+source [find target/renesas_r8a7794.cfg]
+source [find board/renesas_gen2_common.cfg]
diff --git a/tcl/board/renesas_stout.cfg b/tcl/board/renesas_stout.cfg
new file mode 100644
index 0000000..d35f874
--- /dev/null
+++ b/tcl/board/renesas_stout.cfg
@@ -0,0 +1,4 @@
+# Renesas R-Car H2 Evaluation Board
+
+source [find target/renesas_r8a7790.cfg]
+source [find board/renesas_gen2_common.cfg]
diff --git a/tcl/board/st_nucleo_f7.cfg b/tcl/board/st_nucleo_f7.cfg
index 88a8a30..f94679b 100644
--- a/tcl/board/st_nucleo_f7.cfg
+++ b/tcl/board/st_nucleo_f7.cfg
@@ -1,7 +1,7 @@
 # STMicroelectronics STM32F7 Nucleo development board
 # Known boards: NUCLEO-F746ZG and NUCLEO-F767ZI
 
-source [find interface/stlink-v2-1.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/st_nucleo_h743zi.cfg b/tcl/board/st_nucleo_h743zi.cfg
index baedeb6..cfe2cda 100644
--- a/tcl/board/st_nucleo_h743zi.cfg
+++ b/tcl/board/st_nucleo_h743zi.cfg
@@ -1,7 +1,7 @@
 # This is an ST NUCLEO-H743ZI board with single STM32H743ZI chip.
 # http://www.st.com/en/evaluation-tools/nucleo-h743zi.html
 
-source [find interface/stlink-v2-1.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/st_nucleo_l073rz.cfg b/tcl/board/st_nucleo_l073rz.cfg
index fa9dc87..b32f8d5 100644
--- a/tcl/board/st_nucleo_l073rz.cfg
+++ b/tcl/board/st_nucleo_l073rz.cfg
@@ -1,6 +1,6 @@
 # This is an ST NUCLEO-L073RZ board with single STM32L073RZ chip.
 # http://www.st.com/en/evaluation-tools/nucleo-l073rz.html
-source [find interface/stlink-v2-1.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/stm32h7x3i_eval.cfg b/tcl/board/stm32h7x3i_eval.cfg
index 2949ded..caf68b6 100644
--- a/tcl/board/stm32h7x3i_eval.cfg
+++ b/tcl/board/stm32h7x3i_eval.cfg
@@ -4,7 +4,7 @@
 # This is an ST EVAL-H753XI board with single STM32H753XI chip.
 # http://www.st.com/en/evaluation-tools/stm32h753i-eval.html
 
-source [find interface/stlink-v2-1.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/ti_cc13x0_launchpad.cfg b/tcl/board/ti_cc13x0_launchpad.cfg
new file mode 100644
index 0000000..9e1c1ea
--- /dev/null
+++ b/tcl/board/ti_cc13x0_launchpad.cfg
@@ -0,0 +1,7 @@
+#
+# TI CC13x0 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+transport select jtag
+adapter_khz 2500
+source [find target/ti_cc13x0.cfg]
diff --git a/tcl/board/ti_cc13x2_launchpad.cfg b/tcl/board/ti_cc13x2_launchpad.cfg
new file mode 100644
index 0000000..18c5ce5
--- /dev/null
+++ b/tcl/board/ti_cc13x2_launchpad.cfg
@@ -0,0 +1,7 @@
+#
+# TI CC13x2 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter_khz 2500
+transport select jtag
+source [find target/ti_cc13x2.cfg]
diff --git a/tcl/board/ti_cc26x0_launchpad.cfg b/tcl/board/ti_cc26x0_launchpad.cfg
new file mode 100644
index 0000000..3613a47
--- /dev/null
+++ b/tcl/board/ti_cc26x0_launchpad.cfg
@@ -0,0 +1,7 @@
+#
+# TI CC26x0 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter_khz 2500
+transport select jtag
+source [find target/ti_cc26x0.cfg]
diff --git a/tcl/board/ti_cc26x2_launchpad.cfg b/tcl/board/ti_cc26x2_launchpad.cfg
new file mode 100644
index 0000000..2f2b34b
--- /dev/null
+++ b/tcl/board/ti_cc26x2_launchpad.cfg
@@ -0,0 +1,7 @@
+#
+# TI CC26x2 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter_khz 2500
+transport select jtag
+source [find target/ti_cc26x2.cfg]
diff --git a/tcl/board/ti_cc3220sf_launchpad.cfg b/tcl/board/ti_cc3220sf_launchpad.cfg
new file mode 100644
index 0000000..a3dac62
--- /dev/null
+++ b/tcl/board/ti_cc3220sf_launchpad.cfg
@@ -0,0 +1,7 @@
+#
+# TI CC3220SF-LaunchXL LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter_khz 2500
+transport select swd
+source [find target/ti_cc3220sf.cfg]
diff --git a/tcl/board/ti_cc32xx_launchpad.cfg b/tcl/board/ti_cc32xx_launchpad.cfg
new file mode 100644
index 0000000..f657bdf
--- /dev/null
+++ b/tcl/board/ti_cc32xx_launchpad.cfg
@@ -0,0 +1,7 @@
+#
+# TI CC32xx-LaunchXL LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter_khz 2500
+transport select swd
+source [find target/ti_cc32xx.cfg]
diff --git a/tcl/board/ti_msp432_launchpad.cfg b/tcl/board/ti_msp432_launchpad.cfg
new file mode 100644
index 0000000..bfad322
--- /dev/null
+++ b/tcl/board/ti_msp432_launchpad.cfg
@@ -0,0 +1,7 @@
+#
+# TI MSP432 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter_khz 2500
+transport select swd
+source [find target/ti_msp432.cfg]
diff --git a/tcl/board/tp-link_tl-mr3020.cfg b/tcl/board/tp-link_tl-mr3020.cfg
index 7e040b3..48fb698 100644
--- a/tcl/board/tp-link_tl-mr3020.cfg
+++ b/tcl/board/tp-link_tl-mr3020.cfg
@@ -1,39 +1,5 @@
 source [find target/atheros_ar9331.cfg]
 
-proc ar9331_25mhz_pll_init {} {
-	mww 0xb8050008 0x00018004	;# bypass PLL; AHB_POST_DIV - ratio 4
-	mww 0xb8050004 0x00000352	;# 34000(ns)/40ns(25MHz) = 0x352 (850)
-	mww 0xb8050000 0x40818000	;# Power down control for CPU PLL
-					;# OUTDIV | REFDIV | DIV_INT
-	mww 0xb8050010 0x001003e8	;# CPU PLL Dither FRAC Register
-					;# (disabled?)
-	mww 0xb8050000 0x00818000	;# Power on | OUTDIV | REFDIV | DIV_INT
-	mww 0xb8050008 0x00008000	;# remove bypass;
-					;# AHB_POST_DIV - ratio 2
-}
-
-proc ar9331_ddr1_init {} {
-	mww 0xb8000000 0x7fbc8cd0       ;# DDR_CONFIG - lots of DRAM confs
-	mww 0xb8000004 0x9dd0e6a8	;# DDR_CONFIG2 - more DRAM confs
-
-	mww 0xb8000010 0x8	;# Forces a PRECHARGE ALL cycle
-	mww 0xb8000008 0x133	;# mode reg: 0x133 - default
-	mww 0xb8000010 0x1	;# Forces an MRS update cycl
-	mww 0xb800000c 0x2	;# Extended mode register value.
-				;# default 0x2 - Reset to weak driver, DLL on
-	mww 0xb8000010 0x2	;# Forces an EMRS update cycle
-	mww 0xb8000010 0x8	;# Forces a PRECHARGE ALL cycle
-	mww 0xb8000008 0x33	;# mode reg: remove some bit?
-	mww 0xb8000010 0x1	;# Forces an MRS update cycl
-	mww 0xb8000014 0x4186	;# enable refres: bit(14) - set refresh rate
-	mww 0xb800001c 0x8	;# This register is used along with DQ Lane 0,
-				;# DQ[7:0], DQS_0
-	mww 0xb8000020 0x9	;# This register is used along with DQ Lane 1,
-				;# DQ[15:8], DQS_1.
-	mww 0xb8000018 0xff	;# DDR read and capture bit mask.
-				;# Each bit represents a cycle of valid data.
-}
-
 $_TARGETNAME configure -event reset-init {
 	ar9331_25mhz_pll_init
 	sleep 1