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author | Peter Griffin <peter.griffin@linaro.org> | 2017-06-12 16:28:03 +0100 |
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committer | Paul Fertser <fercerpav@gmail.com> | 2017-10-16 14:10:52 +0100 |
commit | 0e02fe40c64ad7488aeb351641723e1eb9ae49cb (patch) | |
tree | e94439461ff9deb0db0da4da894569ecc3368f05 /tcl/board | |
parent | 2168c475ff7ca0f2914bee39700952600014ac40 (diff) | |
download | riscv-openocd-0e02fe40c64ad7488aeb351641723e1eb9ae49cb.zip riscv-openocd-0e02fe40c64ad7488aeb351641723e1eb9ae49cb.tar.gz riscv-openocd-0e02fe40c64ad7488aeb351641723e1eb9ae49cb.tar.bz2 |
tcl: add hi3798 target and Tocoding Poplar board config
This config covers the 4x Cortex A53 CPUs. A custom connector
is required from J14 to standard ARM JTAG on v1 boards. However
v2 hardware should have a standard FTSH-105-01-L-DV connector.
Pinmuxing code to enable JTAG pins is included in l-loader-poplar
repository, so board is flashed with open source code, JTAG
is available at very early boot. Alternatively the following
pokes can be issued from U-Boot to enable JTAG (e.g. to debug
hisilicon SDK).
mw 0xf8a210ec 0x130;
mw 0xf8a210f0 0x130;
mw 0xf8a210f4 0x130;
mw 0xf8a210f8 0x130;
mw 0xf8a210fc 0x130;
mw 0xf8a21100 0x130;
Change-Id: I2b83dfcb3dc5461c1620f94dd99aa7b31fdda59b
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-on: http://openocd.zylin.com/4161
Tested-by: jenkins
Reviewed-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Diffstat (limited to 'tcl/board')
-rw-r--r-- | tcl/board/tocoding_poplar.cfg | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/tcl/board/tocoding_poplar.cfg b/tcl/board/tocoding_poplar.cfg new file mode 100644 index 0000000..fd66156 --- /dev/null +++ b/tcl/board/tocoding_poplar.cfg @@ -0,0 +1,28 @@ +# +# board configuration for Tocoding Poplar +# + +# board does not feature anything but JTAG +transport select jtag + +adapter_khz 10000 + +# SRST-only reset configuration +reset_config srst_only srst_push_pull + +source [find tcl/target/hi3798.cfg] + +# halt the cores when gdb attaches +${_TARGETNAME}0 configure -event gdb-attach "halt" + +# make sure the default target is the boot core +targets ${_TARGETNAME}0 + +proc core_up { args } { + global _TARGETNAME + + # examine remaining cores + foreach _core [set args] { + ${_TARGETNAME}$_core arp_examine + } +} |