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| author | Greg Savin <43152568+SiFiveGregS@users.noreply.github.com> | 2018-11-05 13:39:38 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-11-05 13:39:38 -0800 |
| commit | 6749c70a3ae891552296888986e6eeae1e17f11a (patch) | |
| tree | 584aa6c0ef2e807f1ff4ac3dfcffcb6b776c166d /tcl/board/sifive-e31arty-cjtag.cfg | |
| parent | 874cadca316c05d1b10abc9bd1851c6941264766 (diff) | |
| download | riscv-openocd-6749c70a3ae891552296888986e6eeae1e17f11a.zip riscv-openocd-6749c70a3ae891552296888986e6eeae1e17f11a.tar.gz riscv-openocd-6749c70a3ae891552296888986e6eeae1e17f11a.tar.bz2 | |
Support for two-wire cJTAG OSCAN1 signaling thru FTDI devices with appropriate pinout (#320)
Added support for cJTAG OSCAN1 over FTDI MPSSE.
Diffstat (limited to 'tcl/board/sifive-e31arty-cjtag.cfg')
| -rw-r--r-- | tcl/board/sifive-e31arty-cjtag.cfg | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/tcl/board/sifive-e31arty-cjtag.cfg b/tcl/board/sifive-e31arty-cjtag.cfg new file mode 100644 index 0000000..58ba23a --- /dev/null +++ b/tcl/board/sifive-e31arty-cjtag.cfg @@ -0,0 +1,23 @@ +# +# Be sure you include the speed and interface before this file +# Example: +# -c "adapter_khz 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e31arty-cjtag.cfg" + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913 + + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + oscan1_ftdi_set_signal nSRST 0 + oscan1_ftdi_set_signal nSRST z +} +halt +flash protect 0 64 last off +echo "Ready for Remote Connections" |