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author | Edward Fewell <efewell@ti.com> | 2020-06-03 14:55:07 -0500 |
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committer | Antonio Borneo <borneo.antonio@gmail.com> | 2020-06-14 14:25:07 +0100 |
commit | 11116ef6ad875055a43cf9af1f228991349f2ba1 (patch) | |
tree | 382d461e5bf2c2dc1a6f6adcfdd5cf7ebf2fcada /src | |
parent | b7d41ef96aaf371e71cb58f5fa7104f4a201ea27 (diff) | |
download | riscv-openocd-11116ef6ad875055a43cf9af1f228991349f2ba1.zip riscv-openocd-11116ef6ad875055a43cf9af1f228991349f2ba1.tar.gz riscv-openocd-11116ef6ad875055a43cf9af1f228991349f2ba1.tar.bz2 |
target/icepick.cfg: Add support for Test TAPs in ICEPick C
In addition to the debug TAPs, the ICEPick C also supports
a bank of Test TAPs (limited functionality intended for
non-debuggable targets). Added support for Test TAPs to
the icepick_c_tapenable routine. Port numbers of 0 to 15
will continue to be handled as a debug TAP number. Test
TAPs will be port numbers of 16 to 31.
This functionality will be needed for doing a flash
mass erase on CC26xx/CC13xx targets. It is possible
for user application to block even adding the Cortex M
TAP to the scan chain, so the only way to unbrick the
target and erase the flash is using a component on a
test TAP of the device's ICEPick router.
Change-Id: I0aa52a08d43a00cbd396efdeadd504fc31c98510
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5715
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'src')
0 files changed, 0 insertions, 0 deletions