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| author | Tim Newsome <tim@sifive.com> | 2017-12-11 15:32:01 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-12-19 10:41:48 -0800 |
| commit | 56ad0e5b300c9f2c68637922972e12e6ff2d06dd (patch) | |
| tree | f4c65e986abb0c7a893270bf4e8afbf3edf6cc99 /src | |
| parent | 10c17fdf17548d5ee32ae23023bb62e532bfef03 (diff) | |
| download | riscv-openocd-56ad0e5b300c9f2c68637922972e12e6ff2d06dd.zip riscv-openocd-56ad0e5b300c9f2c68637922972e12e6ff2d06dd.tar.gz riscv-openocd-56ad0e5b300c9f2c68637922972e12e6ff2d06dd.tar.bz2 | |
Avoid another assertion failure.
Change-Id: Ia54f778152974164697b712c360918e17a127d95
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/riscv/riscv-013.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 6083ba8..98a6352 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1193,11 +1193,15 @@ static int examine(struct target *target) RISCV_INFO(r); r->impebreak = get_field(dmstatus, DMI_DMSTATUS_IMPEBREAK); + // Don't call any riscv_* functions until after we've counted the number of + // cores and initialized registers. for (int i = 0; i < RISCV_MAX_HARTS; ++i) { if (!riscv_rtos_enabled(target) && i != target->coreid) continue; - riscv_set_current_hartid(target, i); + r->current_hartid = i; + riscv013_select_current_hart(target); + uint32_t s = dmi_read(target, DMI_DMSTATUS); if (get_field(s, DMI_DMSTATUS_ANYNONEXISTENT)) { break; |