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authorTim Newsome <tim@sifive.com>2018-01-03 12:23:22 -0800
committerTim Newsome <tim@sifive.com>2018-01-09 12:06:11 -0800
commit29c7a767082909bef17d4e3259d9b20da46b6835 (patch)
tree28f2358c930d3ebb22c29897137e95f45f54f0e4 /src
parentfd506fa839892cddf8aab06192f4259fba81037c (diff)
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Muck with mstatus to always be able to read FPRs
Change-Id: I7ff8bde4578c9ddd175c5cca370295c790cfbba7
Diffstat (limited to 'src')
-rw-r--r--src/target/riscv/riscv-013.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index a5b1ee2..9f37089 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -1003,8 +1003,15 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t
/* Write program to move data into s0. */
+ uint64_t mstatus;
if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
- /* TODO: Possibly set F in mstatus. */
+ if (register_read_direct(target, &mstatus, GDB_REGNO_MSTATUS) != ERROR_OK)
+ return ERROR_FAIL;
+ if ((mstatus & MSTATUS_FS) == 0)
+ if (register_write_direct(target, GDB_REGNO_MSTATUS,
+ set_field(mstatus, MSTATUS_FS, 1)) != ERROR_OK)
+ return ERROR_FAIL;
+
if (riscv_supports_extension(target, 'D') && riscv_xlen(target) < 64) {
/* There are no instructions to move all the bits from a
* register, so we need to use some scratch RAM. */
@@ -1042,6 +1049,11 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t
return ERROR_FAIL;
}
+ if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31 &&
+ (mstatus & MSTATUS_FS) == 0)
+ if (register_write_direct(target, GDB_REGNO_MSTATUS, mstatus) != ERROR_OK)
+ return ERROR_FAIL;
+
/* Restore S0. */
if (register_write_direct(target, GDB_REGNO_S0, s0) != ERROR_OK)
return ERROR_FAIL;