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| author | Tim Newsome <tim@sifive.com> | 2017-06-19 10:56:11 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-06-20 11:32:42 -0700 |
| commit | ccdd26e3ef8309e26fcda3581ce87dc4eaeb37b2 (patch) | |
| tree | 1f102951fe272211a8d5fcfe8807c1ec0cdf3a1d /src | |
| parent | 927f9d887379a0af17cc5ab51a008c7ab89007df (diff) | |
| download | riscv-openocd-ccdd26e3ef8309e26fcda3581ce87dc4eaeb37b2.zip riscv-openocd-ccdd26e3ef8309e26fcda3581ce87dc4eaeb37b2.tar.gz riscv-openocd-ccdd26e3ef8309e26fcda3581ce87dc4eaeb37b2.tar.bz2 | |
Comment curious code.
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/riscv/riscv-013.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 9053feb..c411940 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1285,6 +1285,8 @@ static int read_memory(struct target *target, target_addr_t address, size, address); select_dmi(target); + /* There was a bug in the memory system and only accesses from hart 0 actually + * worked correctly. This should be obselete now. -palmer */ riscv_set_current_hartid(target, 0); /* This program uses two temporary registers. A word of data and the @@ -1481,6 +1483,8 @@ static int write_memory(struct target *target, target_addr_t address, LOG_DEBUG("writing %d words of %d bytes to 0x%08lx", count, size, (long)address); select_dmi(target); + /* There was a bug in the memory system and only accesses from hart 0 actually + * worked correctly. This should be obselete now. -palmer */ riscv_set_current_hartid(target, 0); /* This program uses two temporary registers. A word of data and the |