- integrated patch from Magnus Lundin that fixes at91sam7 flash timing bugs and possible endianness problems (big endian hosts)

- correctly write trailing bytes on str7x flashes
- speed up str7x flash writing by offloading the algorithm to the target


git-svn-id: svn://svn.berlios.de/openocd/trunk@95 b42882b7-edfa-0310-969c-e2dbd0fdcd60

6 files changed, 265 insertions, 84 deletions

diff --git a/src/flash/at91sam7.c b/src/flash/at91sam7.c
index dd8bdeb..a8e390a 100644
--- a/src/flash/at91sam7.c
+++ b/src/flash/at91sam7.c
@@ -135,8 +135,7 @@ u32 at91sam7_get_flash_status(flash_bank_t *bank)
 	target_t *target = at91sam7_info->target;
 	u32 fsr;
 	
-	target->type->read_memory(target, MC_FSR, 4, 1, (u8 *)&fsr);
-	fsr = target_buffer_get_u32(target, (u8 *)&fsr);
+	target_read_u32(target, MC_FSR, &fsr);
 	
 	return fsr;
 }
@@ -146,19 +145,15 @@ void at91sam7_read_clock_info(flash_bank_t *bank)
 {
 	at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 	target_t *target = at91sam7_info->target;
-	unsigned long mckr, mcfr, pllr, tmp, status, mainfreq;
-	unsigned int css, pres, mul, div;
+	u32 mckr, mcfr, pllr;
+	unsigned long tmp, mainfreq;
 
 	/* Read main clock freqency register */
-	target->type->read_memory(target, CKGR_MCFR, 4, 1, (u8 *)&mcfr);
+	target_read_u32(target, CKGR_MCFR, &mcfr);
 	/* Read master clock register */
-	target->type->read_memory(target, PMC_MCKR, 4, 1, (u8 *)&mckr);
+	target_read_u32(target, PMC_MCKR, &mckr);
 	/* Read Clock Generator PLL Register  */
-	target->type->read_memory(target, CKGR_PLLR, 4, 1, (u8 *)&pllr);
-
-	pres = (mckr>>2)&0x7;
-	mul = (pllr>>16)&0x7FF;
-	div = pllr&0xFF;
+	target_read_u32(target, CKGR_PLLR, &pllr);
 
 	at91sam7_info->mck_valid = 0;
 	switch (mckr & PMC_MCKR_CSS) {
@@ -180,10 +175,9 @@ void at91sam7_read_clock_info(flash_bank_t *bank)
 	case 3:		/* PLL Clock */
 		if (mcfr & CKGR_MCFR_MAINRDY) 
 		{
-		        target->type->read_memory(target, CKGR_PLLR, 4, 1,
-						  (u8 *)&pllr);
+			target_read_u32(target, CKGR_PLLR, &pllr);
 			if (!(pllr & CKGR_PLLR_DIV))
-			        break; /* 0 Hz */
+				break; /* 0 Hz */
 			at91sam7_info->mck_valid = 1;
 			mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
 			/* Integer arithmetic should have sufficient precision
@@ -211,7 +205,8 @@ void at91sam7_set_flash_mode(flash_bank_t *bank,int mode)
 	at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 	target_t *target = at91sam7_info->target;
 	
-	if (mode && (mode != at91sam7_info->flashmode)) {
+	if (mode && (mode != at91sam7_info->flashmode))
+	{
 		/* Always round up (ceil) */
 		if (mode==1)
 			/* main clocks in 1uS */
@@ -220,16 +215,18 @@ void at91sam7_set_flash_mode(flash_bank_t *bank,int mode)
 			/* main clocks in 1.5uS */
 			fmcn = (at91sam7_info->mck_freq/666666ul)+1;
 
-		/* Only allow fmcn=0 if clock period is > 30 us. */
-		if (at91sam7_info->mck_freq <= 33333333ul)
+		/* Only allow fmcn=0 if clock period is > 30 us = 33kHz. */
+ 		if (at91sam7_info->mck_freq <= 33333ul)
 			fmcn = 0;
-		else
+		/* Only allow fws=0 if clock frequency is < 30 MHz. */
+		if (at91sam7_info->mck_freq > 30000000ul)
 			fws = 1;
 
 		DEBUG("fmcn: %i", fmcn); 
 		fmr = fmcn << 16 | fws << 8;
-		target->type->write_memory(target, MC_FMR, 4, 1, (u8 *)&fmr);
+		target_write_u32(target, MC_FMR, fmr);
 	}
+	
 	at91sam7_info->flashmode = mode;		
 }
 
@@ -245,7 +242,7 @@ u8 at91sam7_wait_status_busy(flash_bank_t *bank, int timeout)
 	
 	DEBUG("status: 0x%x", status);
 
-	if (status&0x0C)
+	if (status & 0x0C)
 	{
 		ERROR("status register: 0x%x", status);
 		if (status & 0x4)
@@ -267,7 +264,7 @@ int at91sam7_flash_command(struct flash_bank_s *bank,u8 cmd,u16 pagen)
 	target_t *target = at91sam7_info->target;
 
 	fcr = (0x5A<<24) | (pagen<<8) | cmd; 
-	target->type->write_memory(target, MC_FCR, 4, 1, (u8 *)&fcr);
+	target_write_u32(target, MC_FCR, fcr);
 	DEBUG("Flash command: 0x%x, pagenumber:", fcr, pagen);
 
 	if (at91sam7_wait_status_busy(bank, 10)&0x0C) 
@@ -282,7 +279,7 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
 {
 	at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 	target_t *target = at91sam7_info->target;
-	unsigned long cidr, mcfr, status;
+	u32 cidr, status;
 	
 	if (at91sam7_info->target->state != TARGET_HALTED)
 	{
@@ -290,7 +287,7 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
 	}
 	
 	/* Read and parse chip identification register */
-	target->type->read_memory(target, DBGU_CIDR, 4, 1, (u8 *)&cidr);
+	target_read_u32(target, DBGU_CIDR, &cidr);
 	
 	if (cidr == 0)
 	{
@@ -471,7 +468,7 @@ int at91sam7_protect_check(struct flash_bank_s *bank)
 	}
 		
 	status = at91sam7_get_flash_status(bank);
-	at91sam7_info->lockbits = status>>16;
+	at91sam7_info->lockbits = status >> 16;
 	
 	return ERROR_OK;
 }
@@ -496,7 +493,6 @@ int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, ch
 		exit(-1);
 	}
 	
-	
 	/* part wasn't probed for info yet */
 	at91sam7_info->cidr = 0;
 	
@@ -532,10 +528,10 @@ int at91sam7_erase(struct flash_bank_s *bank, int first, int last)
 	at91sam7_read_clock_info(bank);	
 	at91sam7_set_flash_mode(bank,2);
 
-        if ((first == 0) && (last == (at91sam7_info->num_lockbits-1)))
-        {
-        	return at91sam7_flash_command(bank, EA, 0);
-        }
+	if ((first == 0) && (last == (at91sam7_info->num_lockbits-1)))
+	{
+		return at91sam7_flash_command(bank, EA, 0);
+	}
 
 	WARNING("Can only erase the whole flash area, pages are autoerased on write");
 	return ERROR_FLASH_OPERATION_FAILED;
@@ -685,6 +681,7 @@ int at91sam7_probe(struct flash_bank_s *bank)
 		WARNING("Cannot identify target as an AT91SAM");
 		return ERROR_FLASH_OPERATION_FAILED;
 	}
+	
 	return ERROR_OK;
 }
 
diff --git a/src/flash/cfi.c b/src/flash/cfi.c
index fb3d4cc..a90093f 100644
--- a/src/flash/cfi.c
+++ b/src/flash/cfi.c
@@ -1003,11 +1003,11 @@ int cfi_erase_check(struct flash_bank_s *bank)
 	{
 		u32 erase_check_code[] =
 		{
-			0xe4d03001,
-			0xe0022003,
-			0xe2511001,
-			0x1afffffb,
-			0xeafffffe
+			0xe4d03001,	/* ldrb r3, [r0], #1	*/
+			0xe0022003, /* and r2, r2, r3 		*/
+			0xe2511001, /* subs r1, r1, #1		*/
+			0x1afffffb,	/* b -4 				*/
+			0xeafffffe	/* b 0 					*/
 		};
 		
 		/* make sure we have a working area */
@@ -1017,8 +1017,13 @@ int cfi_erase_check(struct flash_bank_s *bank)
 		}
 		else
 		{
+			u8 erase_check_code_buf[5 * 4];
+			
+			for (i = 0; i < 5; i++)
+				target_buffer_set_u32(target, erase_check_code_buf + (i*4), erase_check_code[i]);
+			
 			/* write algorithm code to working area */
-			target->type->write_memory(target, cfi_info->erase_check_algorithm->address, 4, 5, (u8*)erase_check_code);
+			target->type->write_memory(target, cfi_info->erase_check_algorithm->address, 4, 5, erase_check_code_buf);
 		}
 	}
 	
diff --git a/src/flash/flash.c b/src/flash/flash.c
index 6f0523d..7d199cf 100644
--- a/src/flash/flash.c
+++ b/src/flash/flash.c
@@ -25,6 +25,7 @@
 #include "command.h"
 #include "log.h"
 #include "target.h"
+#include "time_support.h"
 
 #include <string.h>
 #include <unistd.h>
@@ -526,6 +527,8 @@ int handle_flash_write_command(struct command_context_s *cmd_ctx, char *cmd, cha
 
 	if ((retval = p->driver->write(p, buffer, offset, buf_cnt)) != ERROR_OK)
 	{
+		command_print(cmd_ctx, "failed writing file %s to flash bank %i at offset 0x%8.8x",
+			args[1], strtoul(args[0], NULL, 0), strtoul(args[2], NULL, 0));
 		switch (retval)
 		{
 			case ERROR_TARGET_NOT_HALTED:
@@ -553,14 +556,16 @@ int handle_flash_write_command(struct command_context_s *cmd_ctx, char *cmd, cha
 				command_print(cmd_ctx, "unknown error");
 		}
 	}
+	else
+	{
+		gettimeofday(&end, NULL);	
+		timeval_subtract(&duration, &end, &start);
+		
+		command_print(cmd_ctx, "wrote file %s to flash bank %i at offset 0x%8.8x in %is %ius", args[1], strtoul(args[0], NULL, 0), strtoul(args[2], NULL, 0), duration.tv_sec, duration.tv_usec);
+	}
+	
 	free(buffer);
 	fclose(binary);
 	
-	gettimeofday(&end, NULL);	
-	timeval_subtract(&duration, &end, &start);
-	
-	command_print(cmd_ctx, "wrote file %s to flash bank %i at offset 0x%8.8x in %is %ius", args[1], strtoul(args[0], NULL, 0), strtoul(args[2], NULL, 0), duration.tv_sec, duration.tv_usec);
-	
 	return ERROR_OK;
-
 }
diff --git a/src/flash/str7x.c b/src/flash/str7x.c
index 2e04f6b..8dc00d0 100644
--- a/src/flash/str7x.c
+++ b/src/flash/str7x.c
@@ -172,6 +172,8 @@ int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char
 
 	str7x_build_block_list(bank);
 	
+	str7x_info->write_algorithm = NULL;
+	
 	return ERROR_OK;
 }
 
@@ -181,7 +183,7 @@ u32 str7x_status(struct flash_bank_s *bank)
 	target_t *target = str7x_info->target;
 	u32 retval;
 
-	target->type->read_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&retval);
+	target_read_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), &retval);
 
 	return retval;
 }
@@ -192,7 +194,7 @@ u32 str7x_result(struct flash_bank_s *bank)
 	target_t *target = str7x_info->target;
 	u32 retval;
 
-	target->type->read_memory(target, str7x_get_flash_adr(bank, FLASH_ER), 4, 1, (u8*)&retval);
+	target_read_u32(target, str7x_get_flash_adr(bank, FLASH_ER), &retval);
 	
 	return retval;
 }
@@ -242,14 +244,14 @@ int str7x_protect_check(struct flash_bank_s *bank)
 	target_t *target = str7x_info->target;
 	
 	int i;
-	int retval;
+	u32 retval;
 
 	if (str7x_info->target->state != TARGET_HALTED)
 	{
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	target->type->read_memory(target, str7x_get_flash_adr(bank, FLASH_NVWPAR), 4, 1, (u8*)&retval);
+	target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVWPAR), &retval);
 
 	for (i = 0; i < bank->num_sectors; i++)
 	{
@@ -282,14 +284,17 @@ int str7x_erase(struct flash_bank_s *bank, int first, int last)
 	for (i = first; i <= last; i++)
 		erase_blocks |= (mem_layout[i].reg_offset << i);
 	
+	/* clear FLASH_ER register */	
+	target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
+	
 	cmd = FLASH_SER;
-	target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&cmd);
+	target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
 	
 	cmd = erase_blocks;
-	target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR1), 4, 1, (u8*)&cmd);
+	target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd);
 	
 	cmd = FLASH_SER|FLASH_WMS;
-	target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&cmd);
+	target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
 	
 	while (((retval = str7x_status(bank)) & (FLASH_BSYA1|FLASH_BSYA2))){
 		usleep(1000);
@@ -324,23 +329,26 @@ int str7x_protect(struct flash_bank_s *bank, int set, int first, int last)
 	
 	protect_blocks = 0xFFFFFFFF;
 
-	if( set )
+	if (set)
 	{
 		for (i = first; i <= last; i++)
 			protect_blocks &= ~(mem_layout[i].reg_offset << i);
 	}
+	
+	/* clear FLASH_ER register */	
+	target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
 
 	cmd = FLASH_SPR;
-	target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&cmd);
+	target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
 	
 	cmd = str7x_get_flash_adr(bank, FLASH_NVWPAR);
-	target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_AR), 4, 1, (u8*)&cmd);
+	target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), cmd);
 	
 	cmd = protect_blocks;
-	target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, (u8*)&cmd);
+	target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), cmd);
 	
 	cmd = FLASH_SPR|FLASH_WMS;
-	target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&cmd);
+	target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
 	
 	while (((retval = str7x_status(bank)) & (FLASH_BSYA1|FLASH_BSYA2))){
 		usleep(1000);
@@ -348,6 +356,8 @@ int str7x_protect(struct flash_bank_s *bank, int set, int first, int last)
 	
 	retval = str7x_result(bank);
 	
+	DEBUG("retval: 0x%8.8x", retval);
+	
 	if (retval & FLASH_ERER)
 		return ERROR_FLASH_SECTOR_NOT_ERASED;
 	else if (retval & FLASH_WPF)
@@ -356,6 +366,123 @@ int str7x_protect(struct flash_bank_s *bank, int set, int first, int last)
 	return ERROR_OK;
 }
 
+int str7x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+{
+	str7x_flash_bank_t *str7x_info = bank->driver_priv;
+	target_t *target = str7x_info->target;
+	u32 buffer_size = 8192;
+	working_area_t *source;
+	u32 address = bank->base + offset;
+	reg_param_t reg_params[5];
+	armv4_5_algorithm_t armv4_5_info;
+	int retval;
+	
+	u32 str7x_flash_write_code[] = {
+					/* write:				*/
+		0xe3a04201, /*	mov r4, #0x10000000	*/
+		0xe5824000, /*	str r4, [r2, #0x0]	*/
+		0xe5821010, /*	str r1, [r2, #0x10]	*/
+		0xe4904004, /*	ldr r4, [r0], #4	*/
+		0xe5824008, /*	str r4, [r2, #0x8]	*/
+		0xe4904004, /*	ldr r4, [r0], #4	*/
+		0xe582400c, /*	str r4, [r2, #0xc]	*/
+		0xe3a04209, /*	mov r4, #0x90000000	*/
+		0xe5824000, /*	str r4, [r2, #0x0]	*/
+		            /* busy:				*/
+		0xe5924000, /*	ldr r4, [r2, #0x0]	*/
+		0xe3140016, /*	tst r4, #0x16		*/
+		0x1afffffc, /*	bne busy			*/
+		0xe5924014, /*	ldr r4, [r2, #0x14]	*/
+		0xe31400ff, /*	tst r4, #0xff		*/
+		0x03140c01, /*	tsteq r4, #0x100	*/
+		0x1a000002, /*	bne exit			*/
+		0xe2811008, /*	add r1, r1, #0x8	*/
+		0xe2533001, /*	subs r3, r3, #1		*/
+		0x1affffec, /*	bne write			*/
+					/* exit:				*/
+		0xeafffffe, /*	b exit				*/
+	};
+	
+	u8 str7x_flash_write_code_buf[80];
+	int i;
+	
+	/* flash write code */
+	if (!str7x_info->write_algorithm)
+	{
+		if (target_alloc_working_area(target, 4 * 20, &str7x_info->write_algorithm) != ERROR_OK)
+		{
+			WARNING("no working area available, can't do block memory writes");
+			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+		};
+
+		/* convert flash writing code into a buffer in target endianness */
+		for (i = 0; i < 20; i++)
+			target_buffer_set_u32(target, str7x_flash_write_code_buf + i*4, str7x_flash_write_code[i]);
+			
+		target_write_buffer(target, str7x_info->write_algorithm->address, 20 * 4, str7x_flash_write_code_buf);
+	}
+
+	/* memory buffer */
+	while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
+	{
+		buffer_size /= 2;
+		if (buffer_size <= 256)
+		{
+			/* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
+			if (str7x_info->write_algorithm)
+				target_free_working_area(target, str7x_info->write_algorithm);
+			
+			WARNING("no large enough working area available, can't do block memory writes");
+			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+		}
+	};
+	
+	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+	armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+	armv4_5_info.core_state = ARMV4_5_STATE_ARM;
+	
+	init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
+	init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
+	init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
+	init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
+	init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
+	
+	while (count > 0)
+	{
+		u32 thisrun_count = (count > (buffer_size / 8)) ? (buffer_size / 8) : count;
+		
+		target_write_buffer(target, source->address, thisrun_count * 8, buffer);
+		
+		buf_set_u32(reg_params[0].value, 0, 32, source->address);
+		buf_set_u32(reg_params[1].value, 0, 32, address);
+		buf_set_u32(reg_params[2].value, 0, 32, str7x_get_flash_adr(bank, FLASH_CR0));
+		buf_set_u32(reg_params[3].value, 0, 32, thisrun_count);
+	
+		if ((retval = target->type->run_algorithm(target, 0, NULL, 5, reg_params, str7x_info->write_algorithm->address, str7x_info->write_algorithm->address + (19 * 4), 10000, &armv4_5_info)) != ERROR_OK)
+		{
+			ERROR("error executing str7x flash write algorithm");
+			return ERROR_FLASH_OPERATION_FAILED;
+		}
+	
+		if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00)
+		{
+			return ERROR_FLASH_OPERATION_FAILED;
+		}
+		
+		buffer += thisrun_count * 8;
+		address += thisrun_count * 8;
+		count -= thisrun_count;
+	}
+	
+	destroy_reg_param(&reg_params[0]);
+	destroy_reg_param(&reg_params[1]);
+	destroy_reg_param(&reg_params[2]);
+	destroy_reg_param(&reg_params[3]);
+	destroy_reg_param(&reg_params[4]);
+	
+	return ERROR_OK;
+}
+
 int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 {
 	str7x_flash_bank_t *str7x_info = bank->driver_priv;
@@ -363,44 +490,80 @@ int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 	u32 dwords_remaining = (count / 8);
 	u32 bytes_remaining = (count & 0x00000007);
 	u32 address = bank->base + offset;
-	u32 *wordbuffer = (u32*)buffer;
 	u32 bytes_written = 0;
 	u32 cmd;
 	u32 retval;
+
 	
 	if (str7x_info->target->state != TARGET_HALTED)
 	{
 		return ERROR_TARGET_NOT_HALTED;
 	}
 	
+	if (offset & 0x7)
+	{
+		WARNING("offset 0x%x breaks required 8-byte alignment", offset);
+		return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+	}
+	
 	if (offset + count > bank->size)
 		return ERROR_FLASH_DST_OUT_OF_BANK;
-	
+
+	/* clear FLASH_ER register */	
+	target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
+
+	/* multiple dwords (8-byte) to be programmed? */
+	if (dwords_remaining > 0) 
+	{
+		/* try using a block write */
+		if ((retval = str7x_write_block(bank, buffer, offset, dwords_remaining)) != ERROR_OK)
+		{
+			if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
+			{
+				/* if block write failed (no sufficient working area),
+				 * we use normal (slow) single dword accesses */ 
+				WARNING("couldn't use block writes, falling back to single memory accesses");
+			}
+			else if (retval == ERROR_FLASH_OPERATION_FAILED)
+			{
+				/* if an error occured, we examine the reason, and quit */
+				retval = str7x_result(bank);
+				
+				ERROR("flash writing failed with error code: 0x%x", retval);
+				return ERROR_FLASH_OPERATION_FAILED;
+			}
+		}
+		else
+		{
+			buffer += dwords_remaining * 8;
+			address += dwords_remaining * 8;
+			dwords_remaining = 0;
+		}
+	}
+
 	while (dwords_remaining > 0)
 	{
 		// command
 		cmd = FLASH_DWPG;
-		target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&cmd);
+		target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
 		
 		// address
-		cmd = address;
-		target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_AR), 4, 1, (u8*)&cmd);
+		target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
 		
-		// data byte 1
-		cmd = wordbuffer[bytes_written/4];
-		target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, (u8*)&cmd);
+		// data word 1
+		target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, buffer + bytes_written);
 		bytes_written += 4;
 		
-		// data byte 2
-		cmd = wordbuffer[bytes_written/4];
-		target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, (u8*)&cmd);
+		// data word 2
+		target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, buffer + bytes_written);
 		bytes_written += 4;
 		
 		/* start programming cycle */
-		cmd = FLASH_DWPG|FLASH_WMS;
-		target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&cmd);
+		cmd = FLASH_DWPG | FLASH_WMS;
+		target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
 		
-		while (((retval = str7x_status(bank)) & (FLASH_BSYA1|FLASH_BSYA2))){
+		while (((retval = str7x_status(bank)) & (FLASH_BSYA1 | FLASH_BSYA2)))
+		{
 			usleep(1000);
 		}
 		
@@ -415,25 +578,39 @@ int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 		address += 8;
 	}
 	
-	while( bytes_remaining > 0 )
+	if (bytes_remaining)
 	{
+		u8 last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+		int i = 0;
+				
+		while(bytes_remaining > 0)
+		{
+			last_dword[i++] = *(buffer + bytes_written); 
+			bytes_remaining--;
+			bytes_written++;
+		}
+		
 		// command
-		cmd = FLASH_WPG;
-		target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&cmd);
+		cmd = FLASH_DWPG;
+		target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
 		
 		// address
-		cmd = address;
-		target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_AR), 4, 1, (u8*)&cmd);
+		target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
 		
-		// data byte
-		cmd = buffer[bytes_written];
-		target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, (u8*)&cmd);
+		// data word 1
+		target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, last_dword);
+		bytes_written += 4;
+		
+		// data word 2
+		target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, last_dword + 4);
+		bytes_written += 4;
 		
 		/* start programming cycle */
-		cmd = FLASH_WPG|FLASH_WMS;
-		target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&cmd);
+		cmd = FLASH_DWPG | FLASH_WMS;
+		target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
 		
-		while (((retval = str7x_status(bank)) & (FLASH_BSYA1|FLASH_BSYA2))){
+		while (((retval = str7x_status(bank)) & (FLASH_BSYA1 | FLASH_BSYA2)))
+		{
 			usleep(1000);
 		}
 		
@@ -443,12 +620,8 @@ int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 			return ERROR_FLASH_OPERATION_FAILED;
 		else if (retval & FLASH_WPF)
 			return ERROR_FLASH_OPERATION_FAILED;
-
-		address++;
-		bytes_remaining--;
-		bytes_written++;
 	}
-	
+		
 	return ERROR_OK;
 }
 
diff --git a/src/flash/str7x.h b/src/flash/str7x.h
index fe63b5e..e1d9b2e 100644
--- a/src/flash/str7x.h
+++ b/src/flash/str7x.h
@@ -28,6 +28,7 @@ typedef struct str7x_flash_bank_s
 	int bank1;
 	struct target_s *target;
 	u32 flash_base;
+	working_area_t *write_algorithm;
 } str7x_flash_bank_t;
 
 enum str7x_status_codes
diff --git a/src/openocd.c b/src/openocd.c
index c6ceb6c..39475b9 100644
--- a/src/openocd.c
+++ b/src/openocd.c
@@ -18,7 +18,7 @@
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
 
-#define OPENOCD_VERSION "Open On-Chip Debugger (2006-08-31 15:00 CEST)"
+#define OPENOCD_VERSION "Open On-Chip Debugger (2006-09-07 20:00 CEST)"
 
 #ifdef HAVE_CONFIG_H
 #include "config.h"