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| author | Spencer Oliver <spen@spen-soft.co.uk> | 2012-04-19 15:51:14 +0100 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2012-04-30 13:05:09 +0000 |
| commit | cc4a934d37136dfedfdceeee35aa016e8e781f14 (patch) | |
| tree | 7011bcbba539bd6fea59617e549a22173d8114e9 /src | |
| parent | 2d8c7c510be09188b6c5446264cd8fcaa9c1e75a (diff) | |
| download | riscv-openocd-cc4a934d37136dfedfdceeee35aa016e8e781f14.zip riscv-openocd-cc4a934d37136dfedfdceeee35aa016e8e781f14.tar.gz riscv-openocd-cc4a934d37136dfedfdceeee35aa016e8e781f14.tar.bz2 | |
stlink: support srst reset
This adds the ability to support srst reset for the stlink/v2.
stlink/v1 will fallback to using SYSRESETREQ which is a full reset - including peripherals.
To enable the use of the srst add the following to your cfg:
reset_config srst_only
Change-Id: I570de607c5f370fd6a4abf47360686c9be07bcdd
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/581
Tested-by: jenkins
Reviewed-by: Mathias Küster <kesmtp@freenet.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/stm32_stlink.c | 33 |
1 files changed, 28 insertions, 5 deletions
diff --git a/src/target/stm32_stlink.c b/src/target/stm32_stlink.c index c9ab810..f9daa01 100644 --- a/src/target/stm32_stlink.c +++ b/src/target/stm32_stlink.c @@ -409,19 +409,36 @@ static int stm32_stlink_assert_reset(struct target *target) int res; struct stlink_interface_s *stlink_if = target_to_stlink(target); struct armv7m_common *armv7m = target_to_armv7m(target); + bool use_srst_fallback = true; LOG_DEBUG("%s", __func__); + enum reset_types jtag_reset_config = jtag_get_reset_config(); + + stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DHCSR, DBGKEY|C_DEBUGEN); + stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, VC_CORERESET); + + if (jtag_reset_config & RESET_HAS_SRST) { + jtag_add_reset(0, 1); + res = stlink_if->layout->api->assert_srst(stlink_if->fd, 0); + if (res == ERROR_COMMAND_NOTFOUND) + LOG_ERROR("Hardware srst not supported, falling back to software reset"); + else if (res == ERROR_OK) { + /* hardware srst supported */ + use_srst_fallback = false; + } + } + + if (use_srst_fallback) { + /* stlink v1 api does support hardware srst, so we use a software reset fallback */ + stlink_if->layout->api->write_debug_reg(stlink_if->fd, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ); + } + res = stlink_if->layout->api->reset(stlink_if->fd); if (res != ERROR_OK) return res; - /* virtual assert reset, we need it for the internal - * jtag state machine - */ - jtag_add_reset(1, 1); - /* registers are now invalid */ register_cache_invalidate(armv7m->core_cache); @@ -438,9 +455,15 @@ static int stm32_stlink_assert_reset(struct target *target) static int stm32_stlink_deassert_reset(struct target *target) { int res; + struct stlink_interface_s *stlink_if = target_to_stlink(target); + + enum reset_types jtag_reset_config = jtag_get_reset_config(); LOG_DEBUG("%s", __func__); + if (jtag_reset_config & RESET_HAS_SRST) + stlink_if->layout->api->assert_srst(stlink_if->fd, 1); + /* virtual deassert reset, we need it for the internal * jtag state machine */ |