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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2020-11-22 13:02:32 +0100 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2020-12-05 23:18:33 +0000 |
| commit | b5e015357ad4ae1fbb286f9bf6c22a563ab93eb7 (patch) | |
| tree | 4d4103220b78e3a4bb3567fcab6fade51d441308 /src/target | |
| parent | a56b7291911b4f42718d406dd2de857db4c11e0f (diff) | |
| download | riscv-openocd-b5e015357ad4ae1fbb286f9bf6c22a563ab93eb7.zip riscv-openocd-b5e015357ad4ae1fbb286f9bf6c22a563ab93eb7.tar.gz riscv-openocd-b5e015357ad4ae1fbb286f9bf6c22a563ab93eb7.tar.bz2 | |
mips_mips64: fix minor host endianness bug
Commit 80f1a92bd798 ("mips64: Add generic mips64 target support")
adds a log of the target's program counter in function
mips_mips64_debug_entry() by directly casting the little-endian
buffer in pc->value.
This is going to print an incorrect value on big-endian hosts.
Use the function buf_get_u64() to return the register value.
Not tested on real HW. Issue identified with GCC compiler flag
'-Wcast-align=strict' after change http://openocd.zylin.com/5937/
("target/register: use an array of uint8_t for register's value").
Change-Id: Icbda2b54a03fdec287c804e623f5db4252f9cd2a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 80f1a92bd798 ("mips64: Add generic mips64 target support")
Reviewed-on: http://openocd.zylin.com/5944
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/mips_mips64.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/mips_mips64.c b/src/target/mips_mips64.c index f941af5..0fc0897 100644 --- a/src/target/mips_mips64.c +++ b/src/target/mips_mips64.c @@ -62,7 +62,7 @@ static int mips_mips64_debug_entry(struct target *target) mips_mips64_examine_debug_reason(target); LOG_DEBUG("entered debug state at PC 0x%" PRIx64 ", target->state: %s", - *(uint64_t *)pc->value, target_state_name(target)); + buf_get_u64(pc->value, 0, 64), target_state_name(target)); return ERROR_OK; } |