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author | Megan Wachs <megan@sifive.com> | 2017-05-15 13:33:17 -0700 |
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committer | Palmer Dabbelt <palmer@dabbelt.com> | 2017-05-15 13:36:05 -0700 |
commit | af6e04d5c05d6d9e36b87f90053a65a5c040469d (patch) | |
tree | 809accd1ec70bc3677b203709af3678695dcdbcd /src/target | |
parent | bcf2a16b0d0d186fdfb371ff4e8009251626ee22 (diff) | |
download | riscv-openocd-af6e04d5c05d6d9e36b87f90053a65a5c040469d.zip riscv-openocd-af6e04d5c05d6d9e36b87f90053a65a5c040469d.tar.gz riscv-openocd-af6e04d5c05d6d9e36b87f90053a65a5c040469d.tar.bz2 |
riscv: Remove some compile warnings
Diffstat (limited to 'src/target')
-rw-r--r-- | src/target/riscv/riscv-013.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 5c1bd32..d3c2fd7 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1854,7 +1854,6 @@ int riscv013_dmi_write_u64_bits(struct target *target) void riscv013_reset_current_hart(struct target *target) { RISCV_INFO(r); - RISCV013_INFO(info); select_dmi(target); uint32_t control = dmi_read(target, DMI_DMCONTROL); @@ -1869,7 +1868,6 @@ void riscv013_reset_current_hart(struct target *target) control = set_field(control, DMI_DMCONTROL_HALTREQ, 0); dmi_write(target, DMI_DMCONTROL, control); - return ERROR_OK; } |