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| author | Tim Newsome <tim@sifive.com> | 2018-03-26 16:00:34 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-03-26 16:00:34 -0700 |
| commit | 0c05aafbf83cf38167aae83c6622d3ecb4b80f44 (patch) | |
| tree | e4899c57fbc33d84fd976accbbf76ea382e73b47 /src/target | |
| parent | b6dca68b2e03a1344007939702f1a84faa56343d (diff) | |
| download | riscv-openocd-0c05aafbf83cf38167aae83c6622d3ecb4b80f44.zip riscv-openocd-0c05aafbf83cf38167aae83c6622d3ecb4b80f44.tar.gz riscv-openocd-0c05aafbf83cf38167aae83c6622d3ecb4b80f44.tar.bz2 | |
Fix m*deleg logic.
Change-Id: Ieda035280334f8e7dc78c9fbc2bdbea7c565d2de
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/riscv/riscv.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 073a355..89c0dc7 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -2328,8 +2328,7 @@ int riscv_init_registers(struct target *target) /* "In systems with only M-mode, or with both M-mode and * U-mode but without U-mode trap support, the medeleg and * mideleg registers should not exist." */ - r->exist = (riscv_supports_extension(target, 'S') || - riscv_supports_extension(target, 'U')) && + r->exist = riscv_supports_extension(target, 'S') || !riscv_supports_extension(target, 'N'); break; } |