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| author | Tim Newsome <tim@sifive.com> | 2023-08-30 10:59:54 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-08-30 10:59:54 -0700 |
| commit | 699eecaab434337dc3915171606b0548c48c6d51 (patch) | |
| tree | 8b085ab8885c1db8ee5a17450638e63ad09715ec /src/target | |
| parent | 5efea16944ceb7b0797755f21ee131dc8b3d90c2 (diff) | |
| parent | 0b914fe5ae5f29e5676755286068861dece5ebeb (diff) | |
| download | riscv-openocd-699eecaab434337dc3915171606b0548c48c6d51.zip riscv-openocd-699eecaab434337dc3915171606b0548c48c6d51.tar.gz riscv-openocd-699eecaab434337dc3915171606b0548c48c6d51.tar.bz2 | |
Merge pull request #906 from MarekVCodasip/zero-no-cache
target/riscv: Don't write to zero.
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/riscv/riscv.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index ac48abd..e453742 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -4753,6 +4753,9 @@ unsigned int riscv_count_harts(struct target *target) */ static bool gdb_regno_cacheable(enum gdb_regno regno, bool is_write) { + if (regno == GDB_REGNO_ZERO) + return !is_write; + /* GPRs, FPRs, vector registers are just normal data stores. */ if (regno <= GDB_REGNO_XPR31 || (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) || |