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| author | Megan Wachs <megan@sifive.com> | 2017-05-01 09:42:11 -0700 |
|---|---|---|
| committer | Megan Wachs <megan@sifive.com> | 2017-05-01 09:42:11 -0700 |
| commit | 95a2eb157ab0f1569faf17ecb666b99532755136 (patch) | |
| tree | 7f756c4db23e811466cd27eead50212e1abf53d0 /src/target | |
| parent | 458bb2069943f81d01febebe209b03804e56f129 (diff) | |
| download | riscv-openocd-95a2eb157ab0f1569faf17ecb666b99532755136.zip riscv-openocd-95a2eb157ab0f1569faf17ecb666b99532755136.tar.gz riscv-openocd-95a2eb157ab0f1569faf17ecb666b99532755136.tar.bz2 | |
riscv-013: more consistent parens
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/riscv/riscv-013.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 4a6bbdb..1d526df 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1265,9 +1265,9 @@ static int read_memory(struct target *target, uint32_t address, * program execution mechanism. */ switch (riscv_xlen(target)) { case 64: - riscv_program_write_ram(&program, r_addr + 4, (((riscv_addr_t)(address)) - size) >> 32); + riscv_program_write_ram(&program, r_addr + 4, (((riscv_addr_t) address) - size) >> 32); case 32: - riscv_program_write_ram(&program, r_addr, (riscv_addr_t)(address) - size); + riscv_program_write_ram(&program, r_addr, ((riscv_addr_t) address) - size); break; default: LOG_ERROR("unknown XLEN %d", riscv_xlen(target)); |