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| author | Ian Thompson <ianst@cadence.com> | 2022-11-04 14:54:24 -0700 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2023-03-18 21:56:50 +0000 |
| commit | 904d58c208ab03f09f8d8e7184d49f42f6e16533 (patch) | |
| tree | 288cb3e868be56fdd30d3661196e02b64de4f8c7 /src/target/xtensa/xtensa_debug_module.h | |
| parent | 047b1a8fc237af480e3bab66a9827a358afd7547 (diff) | |
| download | riscv-openocd-904d58c208ab03f09f8d8e7184d49f42f6e16533.zip riscv-openocd-904d58c208ab03f09f8d8e7184d49f42f6e16533.tar.gz riscv-openocd-904d58c208ab03f09f8d8e7184d49f42f6e16533.tar.bz2 | |
target/xtensa: add NX support
- Manual integration of NX support from xt0.2 release
- No new clang static analysis warnings
Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I95b51ccc83e56c0d4dbf09e01969ed6a4a93d497
Reviewed-on: https://review.openocd.org/c/openocd/+/7356
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'src/target/xtensa/xtensa_debug_module.h')
| -rw-r--r-- | src/target/xtensa/xtensa_debug_module.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/target/xtensa/xtensa_debug_module.h b/src/target/xtensa/xtensa_debug_module.h index b382e03..46b2935 100644 --- a/src/target/xtensa/xtensa_debug_module.h +++ b/src/target/xtensa/xtensa_debug_module.h @@ -246,6 +246,7 @@ struct xtensa_dm_reg_offsets { #define OCDDCR_ENABLEOCD BIT(0) #define OCDDCR_DEBUGINTERRUPT BIT(1) #define OCDDCR_INTERRUPTALLCONDS BIT(2) +#define OCDDCR_STEPREQUEST BIT(3) /* NX only */ #define OCDDCR_BREAKINEN BIT(16) #define OCDDCR_BREAKOUTEN BIT(17) #define OCDDCR_DEBUGSWACTIVE BIT(20) @@ -259,6 +260,8 @@ struct xtensa_dm_reg_offsets { #define OCDDSR_EXECBUSY BIT(2) #define OCDDSR_EXECOVERRUN BIT(3) #define OCDDSR_STOPPED BIT(4) +#define OCDDSR_STOPCAUSE (0xF << 5) /* NX only */ +#define OCDDSR_STOPCAUSE_SHIFT (5) /* NX only */ #define OCDDSR_COREWROTEDDR BIT(10) #define OCDDSR_COREREADDDR BIT(11) #define OCDDSR_HOSTWROTEDDR BIT(14) @@ -275,12 +278,24 @@ struct xtensa_dm_reg_offsets { #define OCDDSR_BREAKINITI BIT(26) #define OCDDSR_DBGMODPOWERON BIT(31) +/* NX stop cause */ +#define OCDDSR_STOPCAUSE_DI (0) /* Debug Interrupt */ +#define OCDDSR_STOPCAUSE_SS (1) /* Single-step completed */ +#define OCDDSR_STOPCAUSE_IB (2) /* HW breakpoint (IBREAKn match) */ +#define OCDDSR_STOPCAUSE_B1 (4) /* SW breakpoint (BREAK.1 instruction) */ +#define OCDDSR_STOPCAUSE_BN (5) /* SW breakpoint (BREAK.N instruction) */ +#define OCDDSR_STOPCAUSE_B (6) /* SW breakpoint (BREAK instruction) */ +#define OCDDSR_STOPCAUSE_DB0 (8) /* HW watchpoint (DBREAK0 match) */ +#define OCDDSR_STOPCAUSE_DB1 (9) /* HW watchpoint (DBREAK0 match) */ + +/* LX stop cause */ #define DEBUGCAUSE_IC BIT(0) /* ICOUNT exception */ #define DEBUGCAUSE_IB BIT(1) /* IBREAK exception */ #define DEBUGCAUSE_DB BIT(2) /* DBREAK exception */ #define DEBUGCAUSE_BI BIT(3) /* BREAK instruction encountered */ #define DEBUGCAUSE_BN BIT(4) /* BREAK.N instruction encountered */ #define DEBUGCAUSE_DI BIT(5) /* Debug Interrupt */ +#define DEBUGCAUSE_VALID BIT(31) /* Pseudo-value to trigger reread (NX only) */ #define TRAXCTRL_TREN BIT(0) /* Trace enable. Tracing starts on 0->1 */ #define TRAXCTRL_TRSTP BIT(1) /* Trace Stop. Make 1 to stop trace. */ |