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| author | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2016-11-11 14:39:09 +0100 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2016-12-08 12:24:11 +0000 |
| commit | 53a936afc0092f4a65975d35bab0e10944fad3db (patch) | |
| tree | 351833831b3d652036bc85d07a998ed8df831f76 /src/target/startup.tcl | |
| parent | ab9d92490cf37fb4cbb394f85d7c8385474dff3f (diff) | |
| download | riscv-openocd-53a936afc0092f4a65975d35bab0e10944fad3db.zip riscv-openocd-53a936afc0092f4a65975d35bab0e10944fad3db.tar.gz riscv-openocd-53a936afc0092f4a65975d35bab0e10944fad3db.tar.bz2 | |
Add -defer-examine option to target create command
The '-defer-examine' option to target create allows declaring targets
that are present on the chain, but not fully functional. They will
be skipped by the initial arp_examine as well as arp_examine after
reset.
Manual examine using 'arp_examine' is needed to examine them, with the
idea that some kind of actions is neeed to bring them to a state where
examine will succeed (if at all possible).
In order to allow value less options to target command, I had to relax
the goi.argc check in jim_target_configure().
Change-Id: I9bf4e8d27eb6476dd9353d15f48965a8cfd5c122
Signed-off-by: Esben Haabendal <esben@haabendal.dk>
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3076
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'src/target/startup.tcl')
| -rw-r--r-- | src/target/startup.tcl | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/target/startup.tcl b/src/target/startup.tcl index cf2813b..9bbc6e3 100644 --- a/src/target/startup.tcl +++ b/src/target/startup.tcl @@ -65,7 +65,7 @@ proc ocd_process_reset_inner { MODE } { foreach t $targets { if {![using_jtag] || [jtag tapisenabled [$t cget -chain-position]]} { $t invoke-event examine-start - set err [catch "$t arp_examine"] + set err [catch "$t arp_examine allow-defer"] if { $err == 0 } { $t invoke-event examine-end } @@ -111,6 +111,12 @@ proc ocd_process_reset_inner { MODE } { continue } + # don't wait for targets where examination is deferred + # they can not be halted anyway at this point + if { ![$t was_examined] && [$t examine_deferred] } { + continue + } + # Wait upto 1 second for target to halt. Why 1sec? Cause # the JTAG tap reset signal might be hooked to a slow # resistor/capacitor circuit - and it might take a while @@ -135,6 +141,12 @@ proc ocd_process_reset_inner { MODE } { continue } + # don't wait for targets where examination is deferred + # they can not be halted anyway at this point + if { ![$t was_examined] && [$t examine_deferred] } { + continue + } + set err [catch "$t arp_waitstate halted 5000"] # Did it halt? if { $err == 0 } { |