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| author | Salvador Arroyo <sarroyofdez@yahoo.es> | 2012-11-01 15:45:12 +0100 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2012-11-16 12:40:34 +0000 |
| commit | 9aad563d15da07fdd938014e65c1bbc38fcf3f6c (patch) | |
| tree | dcd1a8e8dfc70582267075ace61ba98cab38464d /src/target/mips_ejtag.c | |
| parent | 47d5f44fe0401746b3239ea43994889c41c0ca5e (diff) | |
| download | riscv-openocd-9aad563d15da07fdd938014e65c1bbc38fcf3f6c.zip riscv-openocd-9aad563d15da07fdd938014e65c1bbc38fcf3f6c.tar.gz riscv-openocd-9aad563d15da07fdd938014e65c1bbc38fcf3f6c.tar.bz2 | |
mips: code clean up in mips_m4k_debug_entry() function
The function mips_ejtag_read_debug() is defined in mips_ejtag.c
and is called only by mips_m4k_debug_entry() for reading the
CP0 debug register. The comment in this function is obviously wrong.
There is a generic function to read CP0 registers with similar code.
A call to mips32_cp0_read() should work in the same way.
The purpose of reading the debug register is to test if the DSS
bit is set and clear the SSt bit.
It is faster and easier if the SSt bit is cleared without any check.
Remark: DSS bit set only means that a debug single-step exception
ocurred, but it is not possible to step over a sdbbp instruction,
in this case DSS will not be set and the SSt bit not cleared by code.
Resume command at another address will step, so really the behavior
is not the same.
Change-Id: Ibd35f80e0f7669976d96f4ed813830cecf587971
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/950
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'src/target/mips_ejtag.c')
| -rw-r--r-- | src/target/mips_ejtag.c | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c index c2bee94..bd7ae14 100644 --- a/src/target/mips_ejtag.c +++ b/src/target/mips_ejtag.c @@ -248,29 +248,6 @@ int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info) return mips32_pracc_exec(ejtag_info, 1, &inst, 0, NULL, 0, NULL, 0); } -int mips_ejtag_read_debug(struct mips_ejtag *ejtag_info, uint32_t* debug_reg) -{ - /* read ejtag ECR */ - static const uint32_t code[] = { - MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(1, 0, 15), /* sw $1,($15) */ - MIPS32_SW(2, 0, 15), /* sw $2,($15) */ - MIPS32_LUI(1, UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $1 = MIPS32_PRACC_PARAM_OUT */ - MIPS32_ORI(1, 1, LOWER16(MIPS32_PRACC_PARAM_OUT)), - MIPS32_MFC0(2, 23, 0), /* move COP0 Debug to $2 */ - MIPS32_SW(2, 0, 1), - MIPS32_LW(2, 0, 15), - MIPS32_LW(1, 0, 15), - MIPS32_B(NEG16(12)), - MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ - }; - - return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, - 0, NULL, 1, debug_reg, 1); -} - int mips_ejtag_init(struct mips_ejtag *ejtag_info) { uint32_t ejtag_version; |