diff options
| author | Drasko DRASKOVIC <drasko.draskovic@gmail.com> | 2011-07-07 17:41:20 +0200 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2011-08-09 23:17:28 +0200 |
| commit | 1be7163408cc6420d85bf990a2dae46c559a12b1 (patch) | |
| tree | 3b352294934e9a83399eb301f406e3883bda8ae9 /src/target/mips32_pracc.h | |
| parent | 800bc9308dfcae950cd95ca287876b60401e7608 (diff) | |
| download | riscv-openocd-1be7163408cc6420d85bf990a2dae46c559a12b1.zip riscv-openocd-1be7163408cc6420d85bf990a2dae46c559a12b1.tar.gz riscv-openocd-1be7163408cc6420d85bf990a2dae46c559a12b1.tar.bz2 | |
mips32: Added CP0 coprocessor R/W routines
This patch adds MIPS32 CP0 coprocessor R/W routines,
as well as adequate commands to use these routines via
telnet interface.
Now is becomes possible to affect CP0 internal registers
and configure CPU directly from OpenOCD.
Diffstat (limited to 'src/target/mips32_pracc.h')
| -rw-r--r-- | src/target/mips32_pracc.h | 41 |
1 files changed, 38 insertions, 3 deletions
diff --git a/src/target/mips32_pracc.h b/src/target/mips32_pracc.h index b207a5b..0c106ba 100644 --- a/src/target/mips32_pracc.h +++ b/src/target/mips32_pracc.h @@ -4,6 +4,9 @@ * * * Copyright (C) 2008 by David T.L. Wong * * * + * Copyright (C) 2011 by Drasko DRASKOVIC * + * drasko.draskovic@gmail.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -35,9 +38,9 @@ #define MIPS32_PRACC_PARAM_OUT_SIZE 0x1000 #define MIPS32_FASTDATA_HANDLER_SIZE 0x80 -#define UPPER16(uint32_t) (uint32_t >> 16) -#define LOWER16(uint32_t) (uint32_t & 0xFFFF) -#define NEG16(v) (((~(v)) + 1) & 0xFFFF) +#define UPPER16(uint32_t) (uint32_t >> 16) +#define LOWER16(uint32_t) (uint32_t & 0xFFFF) +#define NEG16(v) (((~(v)) + 1) & 0xFFFF) /*#define NEG18(v) (((~(v)) + 1) & 0x3FFFF)*/ int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info, @@ -54,4 +57,36 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_ int num_param_in, uint32_t *param_in, int num_param_out, uint32_t *param_out, int cycle); +/** + * \b mips32_cp0_read + * + * Simulates mfc0 ASM instruction (Move From C0), + * i.e. implements copro C0 Register read. + * + * @param[in] ejtag_info + * @param[in] val Storage to hold read value + * @param[in] cp0_reg Number of copro C0 register we want to read + * @param[in] cp0_sel Select for the given C0 register + * + * @return ERROR_OK on Sucess, ERROR_FAIL otherwise + */ +int mips32_cp0_read(struct mips_ejtag *ejtag_info, + uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel); + +/** + * \b mips32_cp0_write + * + * Simulates mtc0 ASM instruction (Move To C0), + * i.e. implements copro C0 Register read. + * + * @param[in] ejtag_info + * @param[in] val Value to be written + * @param[in] cp0_reg Number of copro C0 register we want to write to + * @param[in] cp0_sel Select for the given C0 register + * + * @return ERROR_OK on Sucess, ERROR_FAIL otherwise + */ +int mips32_cp0_write(struct mips_ejtag *ejtag_info, + uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel); + #endif |