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| author | Dongxue Zhang <elta.era@gmail.com> | 2013-09-23 16:27:03 +0800 |
|---|---|---|
| committer | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2017-02-10 13:50:17 +0100 |
| commit | 47b8cf84202bf792cf66fbfa01169e9592236b8a (patch) | |
| tree | d1935dde99235aa94963fbf51b0f8f59f52398d1 /src/target/feroceon.c | |
| parent | 0ecee8326608a070b476a757cf517d0f50b5ca07 (diff) | |
| download | riscv-openocd-47b8cf84202bf792cf66fbfa01169e9592236b8a.zip riscv-openocd-47b8cf84202bf792cf66fbfa01169e9592236b8a.tar.gz riscv-openocd-47b8cf84202bf792cf66fbfa01169e9592236b8a.tar.bz2 | |
target: Add 64-bit target address support
Define a target_addr_t type to support 32-bit and 64-bit addresses at
the same time. Also define matching TARGET_PRI*ADDR format macros as
well as a convenient TARGET_ADDR_FMT.
In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000)
be least invasive by leaving the formatting unchanged apart from the
type;
for generic code adopt TARGET_ADDR_FMT as unified address format.
Don't silently change gdb formatting here, leave that to later.
Add COMMAND_PARSE_ADDRESS() macro to abstract the address type.
Implement it using its own parse_target_addr() function, in the hopes
of catching pointer type mismatches better.
Add '--disable-target64' configure option to revert to previous 32-bit
target address behavior.
Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5
Signed-off-by: Dongxue Zhang <elta.era@gmail.com>
Signed-off-by: David Ung <david.ung.42@gmail.com>
[AF: Default to enabling (Paul Fertser), rename macros, simplify]
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Diffstat (limited to 'src/target/feroceon.c')
| -rw-r--r-- | src/target/feroceon.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/target/feroceon.c b/src/target/feroceon.c index f12e4e4..6b14ab6 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -460,7 +460,7 @@ static int feroceon_examine_debug_reason(struct target *target) } static int feroceon_bulk_write_memory(struct target *target, - uint32_t address, uint32_t count, const uint8_t *buffer) + target_addr_t address, uint32_t count, const uint8_t *buffer) { int retval; struct arm *arm = target->arch_info; @@ -565,7 +565,7 @@ static int feroceon_bulk_write_memory(struct target *target, buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32); if (endaddress != address + count*4) { LOG_ERROR("DCC write failed," - " expected end address 0x%08" PRIx32 + " expected end address 0x%08" TARGET_PRIxADDR " got 0x%0" PRIx32 "", address + count*4, endaddress); retval = ERROR_FAIL; |