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| author | Tim Newsome <tim@sifive.com> | 2019-04-03 12:13:09 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-03 12:13:09 -0700 |
| commit | c089e6ae9a37d134e92a3d40c2be13003ea09d61 (patch) | |
| tree | 748ec4d12228449583b2a4b8bdc8cf6ba825f094 /src/target/dsp563xx.c | |
| parent | c70862c202b3738c062c7080e827dcdd55c94199 (diff) | |
| download | riscv-openocd-c089e6ae9a37d134e92a3d40c2be13003ea09d61.zip riscv-openocd-c089e6ae9a37d134e92a3d40c2be13003ea09d61.tar.gz riscv-openocd-c089e6ae9a37d134e92a3d40c2be13003ea09d61.tar.bz2 | |
Support simultaneous resume using hasel (#364)
* Remove unnecessary 0.11 code.
Don't need need_strict_step anymore now that we have
riscv_hit_watchpoint().
Don't need 32-bit warning in riscv011_resume() now that address is a
target_address_t.
Change-Id: I375c023a7ec9f62d80b037ddb64d14526ba0a3dc
* WIP little refactor working towards hasel support.
Change-Id: Ie0b8dfd9e5ae2e36613fa00e14c3cd32749141bf
* More refactoring.
Change-Id: I083387c2ecff78ddfea3ed5078444732d77b909b
* More refactoring.
Change-Id: Icea1308499492da51354f89e1529353e8385f3a1
* Starting to work towards actual hasel changes.
Change-Id: If0df05ffa66cc58400b4855f9630a8b1bae3030e
* Implement simultaneous resume using hasel.
Change-Id: I97971d7564fdb159d2052393c8b82a2ffaa8833f
* Add support back for targets that don't have hasel.
Change-Id: I6d5439f0615d5d5333127d280e4f2642649a119a
* Make hasel work with >32 harts.
Change-Id: I3c55009d48bfc5dd62e3341df4e4bd21df2fe44f
Diffstat (limited to 'src/target/dsp563xx.c')
0 files changed, 0 insertions, 0 deletions