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| author | Tomas Vanek <vanekt@fbl.cz> | 2018-02-23 00:12:50 +0100 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-04-12 20:49:18 +0100 |
| commit | 81d0b769a65bf15dda2fd51cd4aee50bb0dc16fb (patch) | |
| tree | 5c3639a420ed9616c6d3717e079ace730851be51 /src/target/cortex_m.h | |
| parent | 09076d10dd553dc63f08e74aedb1b6aa030857f9 (diff) | |
| download | riscv-openocd-81d0b769a65bf15dda2fd51cd4aee50bb0dc16fb.zip riscv-openocd-81d0b769a65bf15dda2fd51cd4aee50bb0dc16fb.tar.gz riscv-openocd-81d0b769a65bf15dda2fd51cd4aee50bb0dc16fb.tar.bz2 | |
target/cortex_m: allow setting the type of a breakpoint
Cortex-M target used 'auto_bp_type' mode. The requested type
of breakpoint was ignored and hard (FPB) breakpoints were set in
'code memory area' 0x00000000-0x1fffffff, soft breakpoints were set above
0x20000000.
The code memory area of Cortex-M does not mean the memory is flash and
vice versa. External flash (parallel or QSPI) is usually mapped above
code memory area. Cortex-M7 ITCM RAM is mapped at 0. Kinetis
has a RAM block under 0x20000000 boundary.
Remove 'auto_bp_type' mode, set breakpoints to requested type.
Change 'cortex_m maskisr auto' handling to use a hard temporary
breakpoint everywhere: it can also workaround not working soft breakpoints
on Cortex-M7 with ICache enabled.
Change-Id: I7a9f9464c5e10bfd7f17cba1037ed07a064fa2e8
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4429
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/target/cortex_m.h')
| -rw-r--r-- | src/target/cortex_m.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h index 9500acc..2daf4cb 100644 --- a/src/target/cortex_m.h +++ b/src/target/cortex_m.h @@ -175,7 +175,6 @@ struct cortex_m_common { int fp_code_available; int fp_rev; int fpb_enabled; - int auto_bp_type; struct cortex_m_fp_comparator *fp_comparator_list; /* Data Watchpoint and Trace (DWT) */ |