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| author | Michel Jaouen <michel.jaouen@stericsson.com> | 2011-09-29 17:17:27 +0200 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2011-09-30 09:45:26 +0200 |
| commit | 00ded4eb012006da1f56c0ba39af09cc4a66db07 (patch) | |
| tree | e685a5c60c47e62b68ef3def6619c296a854c756 /src/target/cortex_a.h | |
| parent | ef885d3b2a3001325f525df250dadd570e5d743e (diff) | |
| download | riscv-openocd-00ded4eb012006da1f56c0ba39af09cc4a66db07.zip riscv-openocd-00ded4eb012006da1f56c0ba39af09cc4a66db07.tar.gz riscv-openocd-00ded4eb012006da1f56c0ba39af09cc4a66db07.tar.bz2 | |
armv7a ,cortex a : add L1, L2 cache support, va to pa support
Diffstat (limited to 'src/target/cortex_a.h')
| -rw-r--r-- | src/target/cortex_a.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/target/cortex_a.h b/src/target/cortex_a.h index b49e670..17e44e2 100644 --- a/src/target/cortex_a.h +++ b/src/target/cortex_a.h @@ -63,6 +63,10 @@ struct cortex_a8_common /* Saved cp15 registers */ uint32_t cp15_control_reg; + /* latest cp15 register value written and cpsr processor mode */ + uint32_t cp15_control_reg_curr; + enum arm_mode curr_mode; + /* Breakpoint register pairs */ int brp_num_context; @@ -73,10 +77,8 @@ struct cortex_a8_common /* Use cortex_a8_read_regs_through_mem for fast register reads */ int fast_reg_read; - /* Flag that helps to resolve what ttb to use: user or kernel */ - int current_address_mode; - struct armv7a_common armv7a_common; + }; static inline struct cortex_a8_common * |