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| author | Paul Fertser <fercerpav@gmail.com> | 2014-02-03 01:19:00 +0400 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2014-10-06 11:54:54 +0000 |
| commit | ec9ccaa288491a5ec09da96e07d7cba3aee981c9 (patch) | |
| tree | 6ba5ab07b2b7b0506335c0855d2a3f16a2e66e09 /src/target/cortex_a.c | |
| parent | 9c47dc9e8e49adff93cf8998638410259014513f (diff) | |
| download | riscv-openocd-ec9ccaa288491a5ec09da96e07d7cba3aee981c9.zip riscv-openocd-ec9ccaa288491a5ec09da96e07d7cba3aee981c9.tar.gz riscv-openocd-ec9ccaa288491a5ec09da96e07d7cba3aee981c9.tar.bz2 | |
arm_adi_v5: make dap_lookup_cs_component() traverse subtables and handle multicore
When looking for a debug base address of a core, one should search
through all the ROM tables, not just the top-level one.
This code also assumes that the first found entry (in a depth-first
search) will correspond to core 0, the second to core 1 etc.
The patch is supposed to be an alternative implementation of
http://openocd.zylin.com/#/c/1313/.
Change-Id: Ifc88971a02fe3d9c00d9bf72a822ade5804d4e09
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1920
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'src/target/cortex_a.c')
| -rw-r--r-- | src/target/cortex_a.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 7d58ab3..0393a44 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -2393,14 +2393,19 @@ static int cortex_a_examine_first(struct target *target) uint32_t dbgbase; /* Get ROM Table base */ uint32_t apid; + int32_t coreidx = target->coreid; + LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table", + target->cmd_name); retval = dap_get_debugbase(swjdp, 1, &dbgbase, &apid); if (retval != ERROR_OK) return retval; /* Lookup 0x15 -- Processor DAP */ retval = dap_lookup_cs_component(swjdp, 1, dbgbase, 0x15, - &armv7a->debug_base); + &armv7a->debug_base, &coreidx); if (retval != ERROR_OK) return retval; + LOG_DEBUG("Detected core %" PRId32 " dbgbase: %08" PRIx32, + coreidx, armv7a->debug_base); } else armv7a->debug_base = target->dbgbase; |