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| author | Omair Javaid <omair.javaid@linaro.org> | 2018-01-22 03:26:01 +0500 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-03-10 13:23:48 +0000 |
| commit | a48264414e53d99ffe69df0687abf1effb13be22 (patch) | |
| tree | f113994325915e9ee181c21d68aa159377a69b79 /src/target/armv8.h | |
| parent | b4a01f8cdc943fe03a827513aad2f4df2d2a7399 (diff) | |
| download | riscv-openocd-a48264414e53d99ffe69df0687abf1effb13be22.zip riscv-openocd-a48264414e53d99ffe69df0687abf1effb13be22.tar.gz riscv-openocd-a48264414e53d99ffe69df0687abf1effb13be22.tar.bz2 | |
Support AArch64 SIMD/FP registers read/write
This patch adds support in openOCD to read/write AArch64 SIMD/FP registers.
This patch depends on a previous patch which adds support to generation
of target xml by openOCD with nested architecture defined types. AArch64
SIMD/FP registers assumes various types and to support all types we
implement them as architecture defined type aarch64v which in turn
consists of various architecture defined types. This is compatible with
AArch64-FPU target xml in GDB. Please refer to
binutils-gdb/gdb/features/aarch64-fpu.xml
Change-Id: I7ffb0c21b3c2e08f13720b765408b30aab2a9808
Signed-off-by: Omair Javaid <omair.javaid@linaro.org>
Reviewed-on: http://openocd.zylin.com/4373
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/target/armv8.h')
| -rw-r--r-- | src/target/armv8.h | 63 |
1 files changed, 52 insertions, 11 deletions
diff --git a/src/target/armv8.h b/src/target/armv8.h index 0f3e66f..6525d26 100644 --- a/src/target/armv8.h +++ b/src/target/armv8.h @@ -63,17 +63,52 @@ enum { ARMV8_PC = 32, ARMV8_xPSR = 33, - ARMV8_ELR_EL1 = 34, - ARMV8_ESR_EL1 = 35, - ARMV8_SPSR_EL1 = 36, - - ARMV8_ELR_EL2 = 37, - ARMV8_ESR_EL2 = 38, - ARMV8_SPSR_EL2 = 39, - - ARMV8_ELR_EL3 = 40, - ARMV8_ESR_EL3 = 41, - ARMV8_SPSR_EL3 = 42, + ARMV8_V0 = 34, + ARMV8_V1, + ARMV8_V2, + ARMV8_V3, + ARMV8_V4, + ARMV8_V5, + ARMV8_V6, + ARMV8_V7, + ARMV8_V8, + ARMV8_V9, + ARMV8_V10, + ARMV8_V11, + ARMV8_V12, + ARMV8_V13, + ARMV8_V14, + ARMV8_V15, + ARMV8_V16, + ARMV8_V17, + ARMV8_V18, + ARMV8_V19, + ARMV8_V20, + ARMV8_V21, + ARMV8_V22, + ARMV8_V23, + ARMV8_V24, + ARMV8_V25, + ARMV8_V26, + ARMV8_V27, + ARMV8_V28, + ARMV8_V29, + ARMV8_V30, + ARMV8_V31, + ARMV8_FPSR, + ARMV8_FPCR, + + ARMV8_ELR_EL1 = 68, + ARMV8_ESR_EL1 = 69, + ARMV8_SPSR_EL1 = 70, + + ARMV8_ELR_EL2 = 71, + ARMV8_ESR_EL2 = 72, + ARMV8_SPSR_EL2 = 73, + + ARMV8_ELR_EL3 = 74, + ARMV8_ESR_EL3 = 75, + ARMV8_SPSR_EL3 = 76, ARMV8_LAST_REG, }; @@ -179,6 +214,12 @@ struct armv8_common { int (*read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value); int (*write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value); + /* SIMD/FPU registers read/write interface */ + int (*read_reg_u128)(struct armv8_common *armv8, int num, + uint64_t *lvalue, uint64_t *hvalue); + int (*write_reg_u128)(struct armv8_common *armv8, int num, + uint64_t lvalue, uint64_t hvalue); + int (*examine_debug_reason)(struct target *target); int (*post_debug_entry)(struct target *target); |