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| author | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2016-10-06 16:10:38 +0200 |
|---|---|---|
| committer | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2017-02-10 14:18:34 +0100 |
| commit | 79c4c22e1570cf0d73bacb4d292951e614d0ab2f (patch) | |
| tree | 6cb6994ed741cc88c04c47cbd3bda9144af9f989 /src/target/armv8.h | |
| parent | 2539a323081f046b14ad613b4a163baaf2679a9f (diff) | |
| download | riscv-openocd-79c4c22e1570cf0d73bacb4d292951e614d0ab2f.zip riscv-openocd-79c4c22e1570cf0d73bacb4d292951e614d0ab2f.tar.gz riscv-openocd-79c4c22e1570cf0d73bacb4d292951e614d0ab2f.tar.bz2 | |
aarch64: register access rewrite
All register access is now performed through common read/write
functions, which delegate the actual register access to the
armv8_common object. armv8_common contains function pointers
to direct read and write requests to the respective low-level
functions for each PE state.
The respective read/write functions are selected on debug state
entry.
At the same time, T32 opcodes are now formatted for ITR in
dpmv8_exec_opcode() and the T32_FMTITR macro is removed from global
visibility.
Change-Id: I9eaef017c7cc9e0c531e693c534901bfdbdb842c
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Diffstat (limited to 'src/target/armv8.h')
| -rw-r--r-- | src/target/armv8.h | 46 |
1 files changed, 40 insertions, 6 deletions
diff --git a/src/target/armv8.h b/src/target/armv8.h index 497e482..85845e6 100644 --- a/src/target/armv8.h +++ b/src/target/armv8.h @@ -26,7 +26,7 @@ #include "armv8_dpm.h" enum { - ARMV8_R0, + ARMV8_R0 = 0, ARMV8_R1, ARMV8_R2, ARMV8_R3, @@ -57,11 +57,23 @@ enum { ARMV8_R28, ARMV8_R29, ARMV8_R30, - ARMV8_R31, + ARMV8_SP = 31, ARMV8_PC = 32, ARMV8_xPSR = 33, + ARMV8_ELR_EL1 = 34, + ARMV8_ESR_EL1 = 35, + ARMV8_SPSR_EL1 = 36, + + ARMV8_ELR_EL2 = 37, + ARMV8_ESR_EL2 = 38, + ARMV8_SPSR_EL2 = 39, + + ARMV8_ELR_EL3 = 40, + ARMV8_ESR_EL3 = 41, + ARMV8_SPSR_EL3 = 42, + ARMV8_LAST_REG, }; @@ -162,8 +174,8 @@ struct armv8_common { struct armv8_mmu_common armv8_mmu; /* Direct processor core register read and writes */ - int (*load_core_reg_u64)(struct target *target, uint32_t num, uint64_t *value); - int (*store_core_reg_u64)(struct target *target, uint32_t num, uint64_t value); + int (*read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value); + int (*write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value); int (*examine_debug_reason)(struct target *target); int (*post_debug_entry)(struct target *target); @@ -270,10 +282,32 @@ int armv8_handle_cache_info_command(struct command_context *cmd_ctx, void armv8_set_cpsr(struct arm *arm, uint32_t cpsr); -static inline int armv8_curel_from_core_mode(struct arm *arm) +static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode) { - return (arm->core_mode >> 6) & 3; + switch (core_mode) { + /* Aarch32 modes */ + case ARM_MODE_USR: + return 0; + case ARM_MODE_SVC: + case ARM_MODE_ABT: /* FIXME: EL3? */ + case ARM_MODE_IRQ: /* FIXME: EL3? */ + case ARM_MODE_FIQ: /* FIXME: EL3? */ + case ARM_MODE_UND: /* FIXME: EL3? */ + case ARM_MODE_SYS: /* FIXME: EL3? */ + return 1; + /* case ARM_MODE_HYP: + * return 2; + */ + case ARM_MODE_MON: + return 3; + /* all Aarch64 modes */ + default: + return (core_mode >> 6) & 3; + } } + +void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64); + extern const struct command_registration armv8_command_handlers[]; #endif |