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author | Tim Newsome <tim@sifive.com> | 2019-04-03 12:38:27 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2019-04-03 12:38:27 -0700 |
commit | 79f9672615dfe77d415bdd7a404f1e149e31b16d (patch) | |
tree | 9af22013cb9ef87f97c92a0136d1d88e1b354587 /src/target/armv8.c | |
parent | c089e6ae9a37d134e92a3d40c2be13003ea09d61 (diff) | |
parent | 11a2bfc2bcedfad0ecb1b8d7f68ac7208cd6b8c0 (diff) | |
download | riscv-openocd-79f9672615dfe77d415bdd7a404f1e149e31b16d.zip riscv-openocd-79f9672615dfe77d415bdd7a404f1e149e31b16d.tar.gz riscv-openocd-79f9672615dfe77d415bdd7a404f1e149e31b16d.tar.bz2 |
Merge branch 'master' into from_upstream
Conflicts:
src/flash/nor/at91sam4.c
src/flash/nor/at91sam4l.c
src/flash/nor/at91samd.c
src/flash/nor/ath79.c
src/flash/nor/atsame5.c
src/flash/nor/cfi.c
src/flash/nor/core.c
src/flash/nor/fespi.c
src/flash/nor/kinetis.c
src/flash/nor/kinetis_ke.c
src/flash/nor/lpc2000.c
src/flash/nor/niietcm4.c
src/flash/nor/nrf5.c
src/flash/nor/numicro.c
src/flash/nor/pic32mx.c
src/flash/nor/stm32h7x.c
src/flash/nor/stm32lx.c
src/flash/nor/stmsmi.c
src/flash/nor/tcl.c
src/flash/nor/tms470.c
src/flash/nor/virtual.c
src/flash/nor/xmc4xxx.c
src/rtos/hwthread.c
src/rtos/rtos.c
src/server/gdb_server.c
src/target/riscv/riscv-011.c
src/target/riscv/riscv-013.c
src/target/riscv/riscv.c
src/target/riscv/riscv.h
Change-Id: I9f0f373d45a9e5845bca83ca52e977f727ea4425
Diffstat (limited to 'src/target/armv8.c')
-rw-r--r-- | src/target/armv8.c | 89 |
1 files changed, 81 insertions, 8 deletions
diff --git a/src/target/armv8.c b/src/target/armv8.c index cee837f..c8cfcae 100644 --- a/src/target/armv8.c +++ b/src/target/armv8.c @@ -678,8 +678,8 @@ void armv8_set_cpsr(struct arm *arm, uint32_t cpsr) */ if (arm->cpsr) { buf_set_u32(arm->cpsr->value, 0, 32, cpsr); - arm->cpsr->valid = 1; - arm->cpsr->dirty = 0; + arm->cpsr->valid = true; + arm->cpsr->dirty = false; } /* Older ARMs won't have the J bit */ @@ -1013,6 +1013,72 @@ int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va, return retval; } +COMMAND_HANDLER(armv8_handle_exception_catch_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct armv8_common *armv8 = target_to_armv8(target); + uint32_t edeccr = 0; + unsigned int argp = 0; + int retval; + + static const Jim_Nvp nvp_ecatch_modes[] = { + { .name = "off", .value = 0 }, + { .name = "nsec_el1", .value = (1 << 5) }, + { .name = "nsec_el2", .value = (2 << 5) }, + { .name = "nsec_el12", .value = (3 << 5) }, + { .name = "sec_el1", .value = (1 << 1) }, + { .name = "sec_el3", .value = (4 << 1) }, + { .name = "sec_el13", .value = (5 << 1) }, + { .name = NULL, .value = -1 }, + }; + const Jim_Nvp *n; + + if (CMD_ARGC == 0) { + const char *sec = NULL, *nsec = NULL; + + retval = mem_ap_read_atomic_u32(armv8->debug_ap, + armv8->debug_base + CPUV8_DBG_ECCR, &edeccr); + if (retval != ERROR_OK) + return retval; + + n = Jim_Nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0x0f); + if (n->name != NULL) + sec = n->name; + + n = Jim_Nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0xf0); + if (n->name != NULL) + nsec = n->name; + + if (sec == NULL || nsec == NULL) { + LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02x", edeccr & 0xff); + return ERROR_FAIL; + } + + command_print(CMD_CTX, "Exception Catch: Secure: %s, Non-Secure: %s", sec, nsec); + return ERROR_OK; + } + + while (CMD_ARGC > argp) { + n = Jim_Nvp_name2value_simple(nvp_ecatch_modes, CMD_ARGV[argp]); + if (n->name == NULL) { + LOG_ERROR("Unknown option: %s", CMD_ARGV[argp]); + return ERROR_FAIL; + } + + LOG_DEBUG("found: %s", n->name); + + edeccr |= n->value; + argp++; + } + + retval = mem_ap_write_atomic_u32(armv8->debug_ap, + armv8->debug_base + CPUV8_DBG_ECCR, edeccr); + if (retval != ERROR_OK) + return retval; + + return ERROR_OK; +} + int armv8_handle_cache_info_command(struct command_context *cmd_ctx, struct armv8_cache_common *armv8_cache) { @@ -1452,17 +1518,17 @@ static int armv8_set_core_reg(struct reg *reg, uint8_t *buf) armv8_set_cpsr(arm, (uint32_t)value); else { buf_set_u64(reg->value, 0, reg->size, value); - reg->valid = 1; + reg->valid = true; } } else if (reg->size <= 128) { uint64_t hvalue = buf_get_u64(buf + 8, 0, reg->size - 64); buf_set_u64(reg->value, 0, 64, value); buf_set_u64(reg->value + 8, 0, reg->size - 64, hvalue); - reg->valid = 1; + reg->valid = true; } - reg->dirty = 1; + reg->dirty = true; return ERROR_OK; } @@ -1519,11 +1585,11 @@ static int armv8_set_core_reg32(struct reg *reg, uint8_t *buf) uint64_t value64 = buf_get_u64(buf, 0, 64); buf_set_u64(reg->value, 0, 64, value64); } - reg->valid = 1; - reg64->valid = 1; + reg->valid = true; + reg64->valid = true; } - reg64->dirty = 1; + reg64->dirty = true; return ERROR_OK; } @@ -1675,6 +1741,13 @@ void armv8_free_reg_cache(struct target *target) } const struct command_registration armv8_command_handlers[] = { + { + .name = "catch_exc", + .handler = armv8_handle_exception_catch_command, + .mode = COMMAND_EXEC, + .help = "configure exception catch", + .usage = "[(nsec_el1,nsec_el2,sec_el1,sec_el3)+,off]", + }, COMMAND_REGISTRATION_DONE }; |