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authorAntonio Borneo <borneo.antonio@gmail.com>2018-07-12 16:15:45 +0200
committerMatthias Welwarsky <matthias@welwarsky.de>2018-07-22 09:09:06 +0100
commit42097baf19d4459a57f5224506e59a8347740f19 (patch)
tree4a1baca9fbccae4c4203bb7c923936179eeb298a /src/target/armv7a.h
parentc584686fd1d1dc7d2059e619de90f35516598134 (diff)
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armv7a: read ttbcr and ttb0/1 at every entry in debug state
Commit bfc5c764df145f68835543119865eabe462e19c2 avoids reading ttbcr and ttb0/1 at every virt2phys translation by caching them, and it updates the cached values in armv7a_arch_state(). But the purpose of any (*arch_state)() method, thus including armv7a_arch_state(), is to only print out and inform the user about some architecture specific status. Moreover, to reduce the verbosity during a GDB session, the method (*arch_state)() is not executed anymore at debug state entry (check use of target->verbose_halt_msg in src/openocd.c), thus the state of translation table gets out-of-sync triggering Error: Address translation failure or even using a wrong address in the memory R/W operation. In addition, the commit above breaks the case of armv7r by calling armv7a_read_ttbcr() unconditionally. Fixed by moving in cortex_a_post_debug_entry() the call to armv7a_read_ttbcr() on armv7a case only. Remove the call to armv7a_read_ttbcr() in armv7a_identify_cache() since it is (conditionally) called only in the same procedure cortex_a_post_debug_entry(). Fixes: bfc5c764df14 ("armv7a: cache ttbcr and ttb0/1 on debug state entry") Change-Id: Ifc20eca190111832e339a01b7f85d28c1547c8ba Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4601 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/target/armv7a.h')
-rw-r--r--src/target/armv7a.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 33f6f5d..57779c6 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -194,6 +194,7 @@ int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val);
int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
struct armv7a_cache_common *armv7a_cache);
+int armv7a_read_ttbcr(struct target *target);
extern const struct command_registration armv7a_command_handlers[];