cortex_a: replace cortex_a_check_address function

When accessing memory through the ARM core, privilege levels and mmu
access permissions observed. Thus it depends on the current mode of the
ARM core whether an access is possible or not. the ARM in USR mode can
not access memory mapped to a higher privilege level. This means, if the
ARM core is halted while executing at PL0, the debugger would be
prevented from setting a breakpoint at an address with a higher privilege
level, e.g. in the OS kernel. This is not desirable.

cortex_a_check_address() tried to work around this by predicting if an
access would fail and switched the ARM core to SVC mode. However, the
prediction was based on hardcoded address ranges and only worked for
Linux and a 3G/1G user/kernel space split.

This patch changes the policy to always switch to SVC mode for memory
accesses. It introduces two functions cortex_a_prep_memaccess() and
cortex_a_post_memaccess() which bracket memory reads and writes. These
function encapsulate all actions necessary for preparation and cleanup.

Change-Id: I4ccdb5fd17eadeb2b66ae28caaf0ccd2d014eaa9
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3119
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins

1 files changed, 0 insertions, 7 deletions

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index f3f0ed7..b9320d1 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -172,13 +172,6 @@ static int armv7a_read_ttbcr(struct target *target)
 		  armv7a->armv7a_mmu.ttbr_mask[0],
 		  armv7a->armv7a_mmu.ttbr_mask[1]);
 
-	/* FIXME: default is hard coded LINUX border  */
-	armv7a->armv7a_mmu.os_border = 0xc0000000;
-	if (ttbcr_n != 0) {
-		LOG_INFO("SVC access above %" PRIx32,
-			armv7a->armv7a_mmu.ttbr_range[0] + 1);
-		armv7a->armv7a_mmu.os_border = armv7a->armv7a_mmu.ttbr_range[0] + 1;
-	}
 done:
 	dpm->finish(dpm);
 	return retval;