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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-04 19:21:14 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-04 19:21:14 -0800 |
| commit | 0073e7a69e55eb435fc2e274ba245a27779963e4 (patch) | |
| tree | 137d7a8f1bbdd53cebebdae49e91627679d476c1 /src/target/armv4_5.h | |
| parent | 31e3ea7c19d39589ac9a8b2220331206b6d1e25c (diff) | |
| download | riscv-openocd-0073e7a69e55eb435fc2e274ba245a27779963e4.zip riscv-openocd-0073e7a69e55eb435fc2e274ba245a27779963e4.tar.gz riscv-openocd-0073e7a69e55eb435fc2e274ba245a27779963e4.tar.bz2 | |
ARM: rename ARMV4_5_MODE_* as ARM_MODE_*
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/armv4_5.h')
| -rw-r--r-- | src/target/armv4_5.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h index de1b933..8e2fca2 100644 --- a/src/target/armv4_5.h +++ b/src/target/armv4_5.h @@ -32,15 +32,15 @@ typedef enum armv4_5_mode { - ARMV4_5_MODE_USR = 16, - ARMV4_5_MODE_FIQ = 17, - ARMV4_5_MODE_IRQ = 18, - ARMV4_5_MODE_SVC = 19, - ARMV4_5_MODE_ABT = 23, + ARM_MODE_USR = 16, + ARM_MODE_FIQ = 17, + ARM_MODE_IRQ = 18, + ARM_MODE_SVC = 19, + ARM_MODE_ABT = 23, ARM_MODE_MON = 26, - ARMV4_5_MODE_UND = 27, - ARMV4_5_MODE_SYS = 31, - ARMV4_5_MODE_ANY = -1 + ARM_MODE_UND = 27, + ARM_MODE_SYS = 31, + ARM_MODE_ANY = -1 } armv4_5_mode_t; const char *arm_mode_name(unsigned psr_mode); @@ -91,7 +91,7 @@ struct arm /** * Indicates what registers are in the ARM state core register set. - * ARMV4_5_MODE_ANY indicates the standard set of 37 registers, + * ARM_MODE_ANY indicates the standard set of 37 registers, * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three * more registers are shadowed, for "Secure Monitor" mode. */ |