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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-01 00:48:53 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-01 00:48:53 -0800 |
| commit | 177bbd8891ae737ea7f8c0791a6236f72cedee40 (patch) | |
| tree | ceeef8ae2d729eb5c3d539249f13f019fa300d7c /src/target/armv4_5.h | |
| parent | 209a0197f0c79442a2314199170a957c36c0ddb6 (diff) | |
| download | riscv-openocd-177bbd8891ae737ea7f8c0791a6236f72cedee40.zip riscv-openocd-177bbd8891ae737ea7f8c0791a6236f72cedee40.tar.gz riscv-openocd-177bbd8891ae737ea7f8c0791a6236f72cedee40.tar.bz2 | |
target: "mcr" and "mrc" are ARM-specific
Switch "mrc" and "mcr" commands to be toplevel ARM operations,
as they should initially have been.
Correct the usage message for both commands: it matches ARM
documentation (as one wants!) instead of reordering them to
match the funky mrc() and mcr() method usage (sigh).
For Cortex-A8: restore a line that got accidentally dropped,
so the secure monitor mode shadow registers will show again.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/armv4_5.h')
| -rw-r--r-- | src/target/armv4_5.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h index 822d143..7229a6c 100644 --- a/src/target/armv4_5.h +++ b/src/target/armv4_5.h @@ -112,11 +112,26 @@ struct arm /** Handle for the Embedded Trace Module, if one is present. */ struct etm_context *etm; + /* FIXME all these methods should take "struct arm *" not target */ + int (*full_context)(struct target *target); int (*read_core_reg)(struct target *target, struct reg *reg, int num, enum armv4_5_mode mode); int (*write_core_reg)(struct target *target, struct reg *reg, int num, enum armv4_5_mode mode, uint32_t value); + + /** Read coprocessor register. */ + int (*mrc)(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value); + + /* Write coprocessor register. */ + int (*mcr)(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value); + void *arch_info; }; |