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| author | Niklas Söderlund <niklas.soderlund@ragnatech.se> | 2018-04-07 21:39:45 +0200 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-04-09 20:18:29 +0100 |
| commit | f00d9bb1d7e6d52e62e7cfc402fda96f3544d911 (patch) | |
| tree | 119499504c23dd6482e1a83e618e23f59aa353a4 /src/target/armv4_5.c | |
| parent | 6e356cbfe27c1718d784f7aa36efb483a523fb64 (diff) | |
| download | riscv-openocd-f00d9bb1d7e6d52e62e7cfc402fda96f3544d911.zip riscv-openocd-f00d9bb1d7e6d52e62e7cfc402fda96f3544d911.tar.gz riscv-openocd-f00d9bb1d7e6d52e62e7cfc402fda96f3544d911.tar.bz2 | |
tcl/target: Add Renesas R-Car R8A7791 M2W target
Add configuration for the Renesas R-Car R8A7791 M2W target.
This is an SoC with two Cortex A15 ARMv7a cores, both cores
are supported.
This patch is based on initial submission by Adam Bass and
improvements by Niklas Söderlund.
Change-Id: I297da62b9ce71ad222a401d98e6bcb8502427673
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Adam Bass <adam.bass@renesas.com>
Cc: Niklas Söderlund <niklas.soderlund@ragnatech.se>
Reviewed-on: http://openocd.zylin.com/4485
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/target/armv4_5.c')
0 files changed, 0 insertions, 0 deletions