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| author | Øyvind Harboe <oyvind.harboe@zylin.com> | 2011-10-26 22:26:44 +0200 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2011-10-26 20:36:04 +0000 |
| commit | e6d979eefcc99aeb3f95fab67598af461ef234c1 (patch) | |
| tree | 9bdf599ebfb069ab0b64c4c85434c45526c68af0 /src/target/arm_simulator.c | |
| parent | 2036c2aaae390996f55a8c0cdd8769fbc8933c5a (diff) | |
| download | riscv-openocd-e6d979eefcc99aeb3f95fab67598af461ef234c1.zip riscv-openocd-e6d979eefcc99aeb3f95fab67598af461ef234c1.tar.gz riscv-openocd-e6d979eefcc99aeb3f95fab67598af461ef234c1.tar.bz2 | |
clang: fix warning about use of unitialized variable
this was a false positive, silence it.
Change-Id: I432e0c466c94cf8fd6bbf0ea153c8501a8a261eb
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/126
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'src/target/arm_simulator.c')
| -rw-r--r-- | src/target/arm_simulator.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c index 0a34cfc..1723b43 100644 --- a/src/target/arm_simulator.c +++ b/src/target/arm_simulator.c @@ -519,7 +519,7 @@ static int arm_simulate_step_core(struct target *target, /* load register instructions */ else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH)) { - uint32_t load_address = 0, modified_address = 0, load_value; + uint32_t load_address = 0, modified_address = 0, load_value = 0; uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store.Rn); /* adjust Rn in case the PC is being read */ |